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Lab 8 Outline Presentation Analysis of the term project

Lab 8 Outline Presentation Analysis of the term project Analysis of Block 1 of the term project (using Term Project pages 11 – 16 ) Analysis of Block 6 of the term project (using Term Project pages 38 - 48 ) Implementing a machine player A machine playing strategy

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Lab 8 Outline Presentation Analysis of the term project

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  1. Lab 8 Outline • Presentation • Analysis of the term project • Analysis of Block 1 of the term project (using Term Project pages 11 – 16) • Analysis of Block 6 of the term project (using Term Project pages 38 - 48) • Implementing a machine player • A machine playing strategy • Xilinx sequential circuit components • Individual work • Experiment 5 • Develop the BCD up counter of the Information Gathering Subblock of Machine Player of the Ppm term project CS 2204 Spring 2014

  2. Analysis of the Term Project • Polytechnic Playing Machine, Ppm • The term project is human vs. machine • The black-box view From page 2 of the Term Project Handout CS 2204 Spring 2014

  3. LD0-LD2 on the FPGA board show the current state Ppm Input/output relationship From page 8 of the Term Project Handout Ppm operation diagram CS 2204 Spring 2014

  4. The Ppm Digital SystemPartitioning From page 9 of the Term Project Handout CS 2204 Spring 2014

  5. Digital Systems • A digital systemperformsmicrooperations • A digital systemconsists of digital circuits • A digital system consists of • A data unit (datapath) • It performs microoperations • A control unit • It controls the datapath CS 2204 Spring 2014

  6. Digital Systems • This first partitioning of a digital system is universal • A microprocessor is a digital system • An iPhone is a digital system • A computer is a collection of digital systems CS 2204 Spring 2014

  7. Digital Systems • The Data Unit has registers, ALUs and buses to perform microoperations • Registers keep (store) data (operands and results) • Arithmetic Logic Units (ALUs) perform additions, subtractions, multiplications, ANDS, ORs, etc. • Buses interconnect registers and ALUs CS 2204 Spring 2014

  8. Digital Systems • The Control Unit (Sequencer) • The control unit determines the sequence of microoperations based on the current state and status signals • In each state, it enables the microoperations of that state to happen in the data unit based on the status signals • Microoperations must start at the right time with correct inputs and end at the right time with correct outputs  We should notlose data and we should not use old data • Glitches, gate delays must be accounted for  When we design it, we account for every possible gate delay • The control unit also determines which state is next : Next State CS 2204 Spring 2014

  9. Digital Systems • The Control Unit (Sequencer) • The state register indicates the current state • Logic to generate the control signals and the next state more irregular than the Data Unit From page 11 of the Term Project Handout CS 2204 Spring 2014

  10. Digital Systems • The Control Unit (Sequencer) design • Hardwiring vs microprogramming • Since our Ppm system is simple, we use hardwiring and so we will concentrate on hardwiring from this point on Gate/FF networks = random logic = irregular Memory bits generate control signals and NS Look-up table Highly regular but slower Not as regular as the datapath CS 2204 Spring 2014

  11. Often a decoder is used to generate the control and next state signals Often a counter is used instead of a register since we frequently trace the states sequentially • Digital Systems • The Control Unit (Sequencer) design • Hardwired Control Unit design • First partitioning on the Control Unit • Control Signal generationSubblock • Next State GenerationSubblock CS 2204 Spring 2014

  12. Digital Systems • The Control Unit (Sequencer) design • Hardwired Control Unit design • Often a counter+decoder combination is used in the sequencer If it is state 0,S0is1 Status signals Current state Next state S0 n D0 Control signals Control Signals & Next State Circuits S1 D1 Data n ..... n-to-2n Decoder n-bit up counter Next State Load S2(n-1) D3 clock CS 2204 Spring 2014

  13. 20 23 Block 1 • The Ppm Control Unit • Block 1, the Control Unit (the sequencer) • It controls the Data Unit • It determines the sequence of microoperations • Which microoperation happens when CS 2204 Spring 2014

  14. The Ppm Control Unit • Block 1, the Control Unit (the sequencer) • The control unit determines the sequence of microoperations based on the status signals • Implemented by using the finite-state machine (FSM) technique • Uses hardwiring • Gate and flip-flip networks generate control signals • Partitioned into • Control Signal generationSubblock • Next State GenerationSubblock CS 2204 Spring 2014

  15. The Ppm Control Unit • Block 1, the Control Unit (the sequencer) Hardwired Control Unit Gate and flip-flop networks generate control and next state signals Control Signal Generation Subblock Control signals Next State Generation Subblock Counter- Decoder combination to keep track of the current state CS 2204 Spring 2014

  16. Digital Systems • How can we design a digital system ? • If the digital system is complex • It is the case with real chips, such as microprocessors • Write an HDL program ►VHDL program ►Verilog HDL program CS 2204 Spring 2014

  17. Digital Systems • How can we design a digital system ? • If the digital system is simple • It is the case with our term project • Use the finite state machine (FSM) technique ► We draw a finite-state diagram • One obtains the operation diagram then converts it to a FSM state diagram with same number of states ►Get a finite-state diagram directly from the operation diagram CS 2204 Spring 2014

  18. Register← Source Wire/bus= Source • Digital Systems • How can we design a digital system ? • If the digital system is simple • It is the case with our term project • Use the finite state machine (FSM) technique ► Obtain a high-level state diagram directly from the operation diagram  Use the Register-Transfer Level (RTL) notation ► Obtain the datapath from the high-level state diagram ► Obtain the low-level state diagram from the datapath andhigh-level state diagram ► Obtain the Control Unit CS 2204 Spring 2014

  19. Digital System Design Using FSM • The Data Unit (Datapath) • The data unit performs microoperations based on the control signals • The data unit goes through states • The high-level state diagram indicates the microoperations ► Each state indicates the microoperations to perform in that clock period The Data Unit generates status signals as it performs microoperations ► In each state, the controlsignals indicate which microoperations should happen The low-level state diagram indicates which control signals should be active CS 2204 Spring 2014

  20. Digital System Design Using FSM • The Control Unit (Sequencer) • The control unit determines the sequence of microoperations based on the status signals • The control unit goes through states • Each state has a unique number to identify ► The state register value is the current state number • In each state, it enables the microoperations of that state to happen in the data unit based on the status signals • It generates the control signals and next state signals timely CS 2204 Spring 2014

  21. Digital System Design Using FSM • The Control Unit (Sequencer) • The sequencer is treated as a state machine • A low-level state diagram (with finite number of states) shows which microoperation happens when in terms of control signals • Each state shows ► Which control signal is active ► Which state to go to next based on status signals CS 2204 Spring 2014

  22. Digital System Design Using FSM • On paper • Start with the black box view and the textual input/outputrelationship of the digital system • Convert the textual input/output relationship to an operation diagram • Convert the operation diagram to a high-level state diagram with microoperations with the same number of states • A diagram with finite number of states • From the high-level state diagram, obtain the datapath • From the high-level state diagram and the datapath, obtain the low-level state diagram • Decide about how to implement the control unit (sequencer) • Hardwiring or microprogramming • Hardwiring is acceptable if it is not a complex digital system • It is the case with the Ppm term project CS 2204 Spring 2014

  23. Digital System Design Using FSM • On paper • Implement the sequencer which is treated as a state machine • The low-level state diagram (a state diagram with finite number of states) shows which microoperation happens when • Each state shows ►Which control signal is active ►Which state to go to next based on status signals • Each state has a unique number to identify ►The state register value is the current state • Convert control signal and next state information of the low-level state diagram to sequencer hardware • Place the counter (state register) + decoder combination if hardwiring is used • Obtain Expressions ►Obtain gate networks of the sequencer • Start implementing the circuits on computer • Start drawing the schematics by using the design on paper CS 2204 Spring 2014

  24. Digital System Design Using FSM • Start with the black box view and the textual input/output relationship of the digital system • The Textual Input/Output Relationship • Starting with the Reset state • Input 8 numbers on K in eight successive clock • periods • Determine sequence number of largest number • Output the sequence number of the largest number in 9th clock period and also a one clock period long valid signal • Repeat these every 9 clock periods • Keep the output value at 0 until the next output • value is calculated The black-box view OUT K Digital System 3 8 Clock Valid CS 2204 Spring 2014

  25. Digital System Design Using FSM • Start with the black box view and the textual input/output relationship of the digital system 9 clock period cycle Cp 9 Cp 1 Cp 2 Cp 3 Cp 4 Cp 5 Cp 6 Cp 7 Cp 8 Clock N0 N1 N2 N3 N4 N5 N6 N7 Output Snum Output SNUM Compare Compare Store it Compare Compare Compare Compare Compare & store & store & store & store & store & store & store Output zero until the new result is obtained OUT OUT Valid CS 2204 Spring 2014

  26. Convert the textual input/output relationship to an operation diagram 0 Store 1st number & store SNUM as 0 1 If K > 1st number then store K & update SNUM 2 If K > current largest then store K & update SNUM 3 If K > current largest then store K & update SNUM 4 If K > current largest then store K & update SNUM 5 • After Reset • Input 8 numbers on K • Choose the largest • Determine sequence number (SNUM) of largest number • OutputSNUM in 9th clock period and also a one clock period long valid signal • Repeat every 9 clock periods • Keep the output value at 0 until the next output value is calculated If K > current largest then store K & update SNUM 6 If K > current largest then store K & update SNUM 7 If K > current largest then store K & update SNUM 8 Output SNUM and Valid CS 2204 Spring 2014

  27. Convert the operation diagram to a high-level state diagram with microoperations with the same number of states 0 A  K ; B 0 1 If K > A then A  K & B 1 2 If K > A then A  K & B 2 3 If K > A then A  K & B 3 4 If K > A then A  K & B 4 5 If K > A then A  K & B 5 6 If K > A then A  K & B 6 7 If K > A then A  K & B 7 8 OUT = B ; Valid = 1 CS 2204 Spring 2014

  28. Register • Convert the operation diagram to a high-level state diagram with microoperations with the same number of states 0 A  K ; B 0 1 If K > A then A  K & B 1 2 If K > A then A  K & B 2 3 If K > A then A  K & B 3 4 If K > A then A  K & B 4 5 If K > A then A  K & B 5 6 If K > A then A  K & B 6 7 If K > A then A  K & B 7 8 OUT = B ; Valid = 1 RTL notation Wires CS 2204 Spring 2014

  29. Obtain the datapathfrom the high-level state diagram 0 A  K ; B 0 1 K If K > A then A  K & B 1 SNUM 2 8 Store If K > A then A  K & B 2 3 Clock Store A 3 8 Clock If K > A then A  K & B 3 B 4 A B 3 3 If K > A then A  K & B 4 1 0 Compare Sel 5 3-bit 2-to-1 MUX If K > A then A  K & B 5 AGTB 0 6 3 If K > A then A  K & B 6 Gt OUT 7 Val If K > A then A  K & B 7 8 OUT = B ; Valid = 1 Valid CS 2204 Spring 2014

  30. Obtain the datapathfrom the high-level state diagram K Remember :  Registers need Store signals MUXes need Select signals • ALUs need ALUcontrol signals • Others may need Enable signals • Special signals may be needed SNUM 8 Store 3 Clock Store A 8 Clock B A B 3 3 Registers 1 0 Compare Sel 3-bit 2-to-1 MUX AGTB 0 3 Gt Snum signals Val signal OUT Val Valid CS 2204 Spring 2014

  31. Obtain the low-level state diagram from the high-level state diagram and the datapath 0 Store = 1 ; SNUM = 0 ; Sel = 0 1 SNUM = 1 ; Sel = 0 If Gt == 1 then Store = 1 2 SNUM = 2 ; Sel = 0 ; If Gt == 1 then Store = 1 3 SNUM = 3 ; Sel = 0 ; If Gt == 1 then Store = 1 4 SNUM = 4 ; Sel = 0 ; If Gt == 1 then Store = 1 5 SNUM = 5 ; Sel = 0 ; If Gt == 1 then Store = 1 6 SNUM = 6 ; Sel = 0 ; If Gt == 1 then Store = 1 7 SNUM = 7 ; Sel = 0 ; If Gt == 1 then Store = 1 8 Val = 1 ; Sel = 1 CS 2204 Spring 2014

  32. Decide about how to implement the control unit (sequencer) K OUT Data Unit 8 3 Clock Valid Store Val 3 Gt Sel SNUM Clock Control Unit Six control signals One status signal We use hardwiring since it is a very simple digital system CS 2204 Spring 2014

  33. Convert control signal and next state information of the low-level state diagram to sequencer hardware How do we implement the round robin trace of the states ? 0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8 We need a combination of ►4-bit Up counter ►3-to-8 Decoder To keep track of the current state CS 2204 Spring 2014

  34. Convert control signal and next state information of the low-level state diagram to sequencer hardware Place the counter+decoder combination if hardwiring is used How do we implement the round robin trace of the states ? 0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8 D0 S0 D1 S1 D0 0 STC0 A0 Q0 D2 S2 D1 0 STC1 A1 D2 S3 Q1 D3 We need a combination of ►4-bit Up counter ►3-to-8 Decoder To keep track of the current state 0 3-to-8 Decoder 4-bit up counter D3 0 D4 S4 STC2 A2 Q2 LD STC3 D5 S5 Q3 STC3 Clock D6 S6 We have to load 0 after the count is 8 ! E S7 D7 S8 CS 2204 Spring 2014

  35. Convert control signal and next state information of the low-level state diagram to sequencer hardware • Place the counter+decoder combination if hardwiring is used • Obtain Expressions Store is 1 when it is ► State 0 OR ► (state 1 OR state 2 OR state 1 OR state 3 OR state 4 OR state 5 OR state 6 OR state 7) ANDGt = 1 Store is 1 when it is ► State 0 OR ► (NOT state 8) ANDGt = 1 Store = S0 + (S8Gt) CS 2204 Spring 2014

  36. Convert control signal and next state information of the low-level state diagram to sequencer hardware • Place the counter+decoder combination if hardwiring is used • Obtain Expressions • Obtain gate networks of the sequencer Store Store = S0 + S8Gt S0 Control Unit Gt S8 CS 2204 Spring 2014

  37. Convert control signal and next state information of the low-level state diagram to sequencer hardware • Place the counter+decoder combination if hardwiring is used • Obtain Expressions Sel is 1 when ► It is state 8 Sel = S8 Val is 1 when ► It is state 8 Val = S8 CS 2204 Spring 2014

  38. Convert control signal and next state information of the low-level state diagram to sequencer hardware • Place the counter+decoder combination if hardwiring is used • Obtain Expressions • Obtain gate networks of the sequencer Sel = S8 Val = S8 Sel Val S8 S8 Control Unit CS 2204 Spring 2014

  39. Convert control signal and next state information of the low-level state diagram to sequencer hardware • Place the counter+decoder combination if hardwiring is used • Obtain Expressions SNUM = 0 when it is state 0 SNUM = 1 when it is state 1 SNUM = 2 when it is state 2 SNUM = 3 when it is state 2 SNUM = 4 when it is state 4 SNUM = 5 when it is state 5 SNUM = 6 when it is state 6 SNUM = 7 when it is state 7 SNUM2 = STC2 SNUM1 = STC1 SNUM0 = STC0 CS 2204 Spring 2014

  40. Convert control signal and next state information of the low-level state diagram to sequencer hardware • Place the counter+decoder combination if hardwiring is used • Obtain Expressions • Obtain gate networks of the sequencer SNUM2 = STC2 SNUM1 = STC1 SNUM0 = STC0 SNUM2 SNUM1 SNUM0 STC2 STC1 STC0 Control Unit CS 2204 Spring 2014

  41. Convert control signal and next state information of the low-level state diagram to sequencer hardware Control Unit CS 2204 Spring 2014

  42. Digital System Design Using FSM • Final digital system design on paper • Start implementing the circuits on computer • Start drawing the schematics by using the design on paper Gt Datapath Control Unit CS 2204 Spring 2014

  43. ? ? Block 6 • Machine Play Block, Block 6 • How is it designed ? • Machine player gathers information and then decides • It must have inputs to gather information • The number of inputs depends on the strategy • But, a few inputs are required for some strategies • It must have outputs to be able to play the game • The number of outputs depends on the strategy • But, a few outputs are required for any strategy CS 2204 Spring 2014

  44. ? ? Block 6 • Machine Play Block, Block 6 • How is it designed ? • Machine player gathers information and then decides • It must have a subblock to gather information • Information gathering is a major operation • It must have a subblock to decide how to play • Decision making is another major operation • Any other subblock (major operation) ? CS 2204 Spring 2014

  45. Machine Play Block, Block 6 • The machine player is active in state 4 to think and play/skip • Machine player stays at least one clock period in state 4 to gather information and decide • It stays more than one clock period if gathering information is done sequentially • Because the information needed is not available all at once and so must be collected one by one • Collecting information in parallel requires a lot of hardware ! • The loop-back arrow indicates that more than once clock period is spent in state 4 CS 2204 Spring 2014

  46. Machine Play Block, Block 6 • The machine player is active in state 4 to think and play/skip • Machine player stays at least one clock period in state 4 to gather information and decide • It stays more than one clock period if gathering information is done sequentially • It collects the information in a number of clock periods and then in one more clock period it plays • The course web site machine player is like that • It collects information for 8 clock periods and decides to play/skip in the 9th clock period ! CS 2204 Spring 2014

  47. Machine Play Block, Block 6 • The machine player is active in state 4 to think and play/skip • The course web site machine player collects information for 8 clock periods and decides to play/skip in the 9th clock period ! CS 2204 Spring 2014

  48. Machine Play Block, Block 6 • The machine player is active in state 4 to think and play/skip • Machine player stays at least one clock period in state 4 to gather information and decide • It stays more than one clock period if gathering information is done sequentially • We need a controlling major operation to determine the sequence of information gathering and then deciding ! • A controller subblock is needed in addition to the information gathering and decision making blocks ! • Since the machine player is a complex sequential circuit with a controller then Block 6 is a tiny digital system itself CS 2204 Spring 2014

  49. Machine Play Block, Block 6 • The machine player is active in state 4 to think and play/skip • Machine player stays at least one clock period in state 4 to gather information and decide • A controller subblock is needed in addition to the information gathering and decision making blocks ! • Since the machine player is a complex sequential circuit with a controller then Block 6 is a tiny digital system itself Information Gathering Decision Making Data Unit Block 6 Sequencing Control Unit CS 2204 Spring 2014

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