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Lattice Verilog Training Part II Jimmy Gao

Lattice Verilog Training Part II Jimmy Gao. Lattice Specific Design by Verilog. Global OE Polarity. Global OE. Multi-Polarity OEs Design not fit for Single-OE Lattice CPLD Architecture; All Global OE must has the same Polarity assign q1 = oe1? qint1 : 8’bZZZZZZZZ;

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Lattice Verilog Training Part II Jimmy Gao

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  1. Lattice Verilog Training Part II Jimmy Gao

  2. Lattice Specific Design by Verilog

  3. Global OE Polarity Global OE Multi-Polarity OEs Design not fit for Single-OE Lattice CPLD Architecture; All Global OE must has the same Polarity assign q1 = oe1? qint1 : 8’bZZZZZZZZ; // q2 = (!oe2)? qint2 : 8’bZZZZZZZZ; assign q2 = oe1? qint2 : 8’bZZZZZZZZ; GLB # 0 GLB # 16 Lattice Single Global OE CPLD Architecture

  4. Lattice Specific - Global OE • For Lattice 1K, 2K, 3K and 6K single Global OE architecture device, simply lock the OE signal to the Global OE pin in the Fitter in order to use the Global OE available in the CPLD. • If the OE controls several different outputs in the design, ensure that the polarity of OE controls are the same and identical to the polarity of Global OE in the Lattice CPLD.

  5. Global Reset Polarity Multi-Polarity Resets Design not fit for Single-Reset Lattice CPLD Architecture. All Global reset must has the same polarity. always @ (posedge clk orposedge reset) begin if ( reset) qint1 = 8’h00; else if ( clk ) qint1 = d; end // wire reset = ! input_reset; // Negative Asserted Reset always (posedge clk orposedge reset ) begin if ( reset ) qint2 = 8’h00; else if ( clk ) qint2 = d; end reset GLB # 0 GLB # 16 Lattice Single Global Reset CPLD Architecture

  6. Lattice Specific - Global Reset • To use the Global Reset pin in the Lattice 1K, 2K, 3K and 6K CPLD, ensure that ALL reset signals in the ENTITY have the same reset name. • Keep in mind that ALL registers have implied resets that connect to the Global Reset pin. If you specify a reset signal in your design, then you need to specify a reset signal for EVERY register and latch used. Otherwise, the Fitter will assign it to a PT reset. • In the Fitter, you must specify to “use Global Reset”

  7. Global Reset and PT Reset Lattice CPLD Architecture has both PT reset and Global reset. always @ (posedge clk ) begin qint1 = d; // Tired to Default Global Reset end always (posedge clk orposedge reset ) begi if ( reset ) qint2 = 8’h00; else if ( clk ) qint2 = d; end GLB # 0 “reset” is PT reset if it not assigned to Global reset. “reset” can be assigned to Global reset in the fitter. PT reset Global reset GLB # 16 Lattice CPLD PT Reset and Global Reset

  8. Lattice Specific - Lattice Macros • Lattice Macros are “hard” macros, which are optimized to the CPLD architecture and will give the best area utilization and best speed performance. • Verilog synthesis, without the use of Lattice Macros, will produce functionally correct models. However, may not yield optimum performance. • Lattice Verilog Macros Library for Synplicity Design • File Lattice .v is located in the <synplcty>\lib\cpld directory

  9. Lattice Specific - Wide XORs // This design example shows 8-input XOR gate module widexor(a, yout); input [7:0] a; output yout; assign yout = a[0]^a[1]^a[2]^a[3]^a[4]^a[5]^a[6]^a[7]; endmodule // include the Lattice Verilog Library // c:\synplcty\lib\cpld\lattice.v in the synthesizing list // refer to Lattice Hard Macro XOR8 // module XOR8(Z0,A0,A1,A2,A3,A4,A5,A6,A7); //synthesis black_box // input A0, A1, A2, A3, A4, A5, A6, A7; output Z0; endmodule module widexor(a, yout); input [7:0] a; output yout; XOR8 x1(yout, a[0],a[1],a[2],a[3],a[4],a[5],a[6],a[7]); endmodule • The above design works, but uses 2 GLB levels. Using the Lattice “hard” Macro for an 8-input XOR gate (xor8) results in 1 GLB level.

  10. Lattice Specific - IO Cell as a Register • Verilog file is similar to any Register description moduleioreg (…); ………… always @ (posedge clka or posedge rset) begin if (rset ) qout = 1’b0; else begin if (clka) qout = qin; end end endmodule • A “property file” is created to direct the Register to the IO Cell and is used in the Fitter # This is a property file to go with a Verilog design with entity IOREG # It assigns a register to a IO Cell Register # The instance name “qoutFD21” is taken from the EDIF netlist PROPERTY IOREG INST qoutFD21 REGTYPE IOC ENDPROPERTY (edif IOREG (edifVersion 2 0 0) (edifLevel 0) ……………… (instance qoutFD21 (viewRef prim (cellRef FD21 (libraryRef lattice)))) ………………

  11. Lattice Specific - IO Cell as a Register • Verilog file is similar to any Register description Use Lattice Hard Macro “ID21”. // module ID21 (Q0, XI0, CLK); // output Q0; // input XI0, CLK; // endmodule module ioreg (qout, qin, clock); output qout; input qin, clock; ID21 reg1 (.Q0(qout), .XI0(qin), .CLK(clock)); endmodule • Use Lattice input register hard macro ID11, ID14, ID18, ID21, ID24 and ID28 to implement the IO Cell register.

  12. Lattice Specific - Input Reg or Bi-directional Input Reg module BIID11 ( Q0, XB0, A, CLK, OE); inout XB0; input A, CLK, OE; output Q0; endmodule module ID11 ( Q0, XI0, CLK); input XI0, CLK; output Q0; endmodule OE A XB0 Q0 D Q CLK Bi-Directional Input Register BIID11, BIID14, …. BIID88 XI0 Q0 D Q CLK Input Register ID11, ID14, … ID28

  13. Lattice Specific - IO Cell as a Latch • Verilog file is similar to any D-type Latch description Use Lattice Hard Macro “IL21”. // module IL21 (Q0, XI0, G); // output Q0; // input XI0, G; // endmodule module iolatch (qout, qin, le); output qout; input qin, le; IL21 Latch1 (.Q0(qout), .XI0(qin), .G(le)); endmodule • Use Lattice input latch hard macro IL11, IL14, IL18, IL21, IL24 and IL28 to implement the IO Cell Latches.

  14. Lattice Specific - Input Latch or Bi-dir Input Latch module BIIL11 ( Q0, XB0, A, G, OE); inout XB0; input A, OE, G; output Q0; endmodule module IL11 ( Q0, XI0, G); input XI0, G; output Q0; endmodule OE A XB0 Q0 D Q G Bi-Directional Input Latch BIIL11, BIIL14, …. BIIL88 XI0 Q0 D Q G Input Latch IL11, IL14, … IL28

  15. Lattice Specific - Pin Numbers • Pin numbers can be assigned in a PIN file (.ppn) or a PROPERTY file (.prp) or directly in the Fitter. • PIN file is attached to the design during compilation with the Lattice fitter. • PIN file syntax: <pin_name> <pin_direction> <pin_number> • Example of PIN file (example.ppn) : oe out 15 clk in 21 enable in 7 bus0 bidi 2 bus1 bidi 3 bus2 bidi 4

  16. Lattice Specific - Pin Numbers (cont’d) • PROPERTY file is attached to the design in the Fitter • PROPERTY file syntax: PROPERTY <cell_name> PIN <pin_name> LOCK <pin_number> ENDPROPERTY • PROPERTY file example (example.prp) : PROPERTY mux PIN A0 LOCK 7 ENDPROPERTY PROPERTY mux PIN A1 LOCK 21 ENDPROPERTY PROPERTY mux PIN A2 LOCK 22 ENDPROPERTY PROPERTY mux PIN B0 LOCK 32 ENDPROPERTY PROPERTY mux PIN B1 LOCK 2 ENDPROPERTY PROPERTY mux PIN B2 LOCK 3 ENDPROPERTY PROPERTY mux PIN clk2 LOCK 10 ENDPROPERTY

  17. Synplicity/Lattice Specific Design Attributes • Pin/Port Attribute Example: module demo ( sysioclk, rst, I, …); //Set IO Cell Clock input sysioclk; /* synthesis clk=ioclk0 */ input rst; input [0:1] I; ………… ………… endmodule Signal Attribute: clk=“ioclk0” sysioclk

  18. Synplicity/Lattice Specific Design Attributes u_ioclK0 • Symbol Attribute module demo (………); ……… wire [0:1] iregs_bk; ………… // Lock Registers as IO Cell Registers FD21 u_ioclk0(iregs_bk(0),i(0),sysioclk,clr); /*synthesis regtype=ioc*/ FD21 u_ioclk1(iregs_bk(1),i(1),sysioclk,clr); /*synthesis regtype=ioc*/ … … endmodule Symbol Attribute: Regtype=“IOC” u_ioclK1 Symbol Attribute: Regtype=“IOC”

  19. Lab Three - Input Registers & Property File Please Turn to your Verilog Lab Book for the Verilog Design Lab No. Three

  20. Lattice Attributes & Property File

  21. External Pin Attributes

  22. Net Attributes

  23. Symbol or Instance Attributes

  24. Pin Attribute in Property File • CRIT • PROPERTY cell_name PIN pin_name CRIT ENDPROPERTY • LOCK • PROPERTY cell_name PIN pin_name LOCK pin_number ENDPROPERTY • PULLUP • PROPERTY cell_name PIN pin_name PULLUP ON ENDPROPERTY • OPENDRAIN • PROPERTY cell_name PIN pin_name OPENDRAIN ON ENDPROPERTY • SLOWSLEW • PROPERTY cell_name PIN pin_name SLOWSLEW ON ENDPROPERTY

  25. Net Attributes in Property File • CLK • PROPERTY cell_name NET net_name CLK CLK0|CLK1|CLK2|IOCLK0|IOCLK2|FASTCLK|SLOWCLK ENDPROPERTY • GROUP • PROPERTY cell_name NET net_name GROUP group_name ENDPROPERTY • PRESERVE • PROPERTY cell_name NET net_name PRESERVE ENDPROPERTY • SAP/EAP • PROPERTY cell_name NET net_name SAP path_name ENDPROPERTY • PROPERTY cell_name NET net_name EAP path_name ENDPROPERTY • SCP/ECP • PROPERTY cell_name NET net_name SCP path_name ENDPROPERTY • PROPERTY cell_name NET net_name ECP path_name ENDPROPERTY • SNP/ENP • PROPERTY cell_name NET net_name SNP path_name ENDPROPERTY • PROPERTY cell_name NET net_name ENP path_name ENDPROPERTY

  26. Symbol or Instance Attributes in Property File • OPTIMIZE • PROPERTY cell_name INST instance_name OPTIMIZE ON ENDPROPERTY • PROPERTY cell_name SYM OPTIMIZE ON ENDPROPERTY • PROTECT • PROPERTY cell_name INST instance_name PROTECT ENDPROPERTY • PROPERTY cell_name SYM PROTECT ENDPROPERTY • REGTYPE • PROPERTY cell_name INST instance_name REGTYPE GLB|IOC ENDPROPERTY • PROPERTY cell_name SYM REGTYPE GLB|IOC ENDPROPERTY • LXOR2 • PROPERTY cell_name INST instance_name LXOR2 ENDPROPERTY • PROPERTY cell_name SYM LXOR2 ENDPROPERTY

  27. State Machine Design Example

  28. ready.burst State Machine Example idle ready bus_id=8’hF3? ready decision read1 read_write read_write ready.burst write read2 ready read3 ready read4

  29. State Machine Example //state machine example module exstate(clock,rst,bus_id,ready,read_write,burst,next_state); input clock, rst, ready, read_write, burst; input [7:0] bus_id; output [7:0] next_state; reg [7:0] next_state; parameter // these parameters represent state names and state encoding // The state encoding style is one-hot encoding idle = 8’h01, decision = 8’h02, read1 = 8’h04, read2 = 8’h08, read3 = 8’h10, read4 = 8’h20, write = 8’h40;

  30. State Machine Example(cont'd) always@(posedge clock orposedge rst) begin if (rst) next_state = idle; else begin case (next_state) idle: if (bus_id == 8’b11110011) next_state = decision; else next_state = idle; decision:if (read_write == 1’b1) next_state = read1; else next_state = write; read1: if (ready == 1’b1 && burst == 1’b0) next_state = idle; else if (ready == 1’b1 && burst == 1’b1) next_state = read2; else next_state = read1;

  31. State Machine Example(cont'd) read2: if (ready == 1’b1) next_state = read3; else next_state = read2; read3: if (ready == 1’b1) next_state = read4; else next_state = read3; read4: if (ready == 1’b1) next_state = idle; else next_state = read4; write: if (ready == 1’b1) next_state = idle; else next_state = write; default: next_state = idle; endcase end // end Else block end // end always block endmodule

  32. State Encoding parameter Idle= xx, Decision= xx, Read= xx, Write= xx;

  33. CPLD Optimization - State Encoding • Many FPGA Verilog implementations use “one-hot” encoding. “One-hot” uses a register for each device state (state-per-bit), with only one register active (or “hot”) at a time. • Use “maximal” encoding for CPLDs it is typically faster and results in better device utilization • Don’t leave optimization solely to your tools; understand your device-architecture characteristics and tailor your design accordingly

  34. CPLD Optimization - State Encoding (cont’d) • Many tool sets, both silicon-vendor-supplied and third-party-developed support not only Mealy and Moore but also “one-hot” state-machine generation. • Some tools automatically select an optimum state machine in response to your circuit implementation, guidance, or both (for example, prioritizing performance to the compiler), whereas other tools always default to one method unless you override them

  35. CPLD Optimization - Undefined States • When all values are not explicitly defined, synthesis results may be unexpected. • Whether using if-else or case statements, not defining all possible values or states can result in unwanted “Latches” Example: parameter // these parameters represent state names idle = 3’b000, decision = 3’b001, read1 = 3’b010, read2 = 3’b011, read3 = 3’b100, read4 = 3’b101, write = 3’b110; Binary Encoding: Idle Decision Read1 Read2 Read3 Read4 Write 3b’000 3’b001 3’b010 3’b011 3’b100 3’b101 3’b110 Undefined State: 3’b111 Action: Use else or Default

  36. Lab Four - State Machine Design, GDX Design & Design Projects Please Turn to your Verilog Lab Book for the Verilog Design Lab No. Four

  37. More on Verilog

  38. initial block • initial block is used in Verilog Simulation Test Bench. initial block : The sequential block similar to always block syntax: initial begin <statements>; end initial block is executed only once in simulation, but always block is executed all the time.

  39. Loops - While, For, Repeat, Forever • All loop statements must be grouped inside the always or initial block. integer counter; integer count; initial initial begin count = 0; begin while ( count < 128 ) for(count=0; count <128; count = count+1) // execute loop till 127. begin // Exit at count 128 $display(“count =%d”, count); begin end $display(“count = %d”, count); end end end While Loop For Loop

  40. Loops - While, For, Repeat, Forever • All loop statements must be grouped inside the always or initial block. integer counter; reg clock; initial initial begin count = 0; begin repeat ( 128) clock = 1’b0; // execute loop 128 times. forever #10 clock = ~clock; begin $display(“count = %d”, count); end end end Repeat Loop Forever Loop

  41. Task • Commonly used Verilog routine that is defined in a Verilog module and also local to the module. • Task can pass multiple values through output and inout argument. module operation; …………. reg [15:0] A, B; reg [15:0] AB_AND, AB_OR, AB_XOR; always @( A or B ) begin // invoke the task bitwise_oper bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B); end …………… //define Task bitwise_oper task bitwise_oper; output [15:0] ab_and, ab_or, ab_xor; // outputs from the task input [15:0] a, b; // input to the task begin #10 ab_and = a & b; ab_or = a | b; ab_xor = a ^ b; end endtask …………….. endmodule Task ab_and[15:0] a[15:0] ab_or[15:0] bitwise_oper b[15:0] ab_xor[15:0]

  42. Function • Commonly used Verilog routine that is defined in a Verilog module and also local to the module. • Function always return a single value. module parity; …………. reg [31:0] addr; reg parity; always @( addr ) begin // invoke the function calc_parity twice parity = calc_parity(addr); $display(“Parity calculated= %b”, calc_parity(addr)); end …………… //define Function calc_parity function calc_parity; input [31:0] address; begin // return the xor of all address bits. calc_parity = ^address; end endfunction …………….. endmodule Function address[31:0] parity calc_parity

  43. Verilog Compiler Directive

  44. `timescale • Use to define time delay values by using certain time unit in Verilog Simulation. • Format: • `timescale <reference_time_unit> / <time_precision> • Example: //Define a time scale for the module dummy_test_bench //Reference time unit is 100 nanoseconds and precision is 1 ns `timescale 100 ns / 1 ns module dummy_test_bench; reg toggle; wire clk_out; clk_bk myclk (.clkin(toggle), .clkout(clk_out); initial toggle = 1’b0; always #5 // Flip toggle every 5 time units toggle = ~toggle; // 5 time units = 500 ns = 0.5 us endmodule

  45. `define • Use to define text macro in Verilog like `define <macro_name>. • The Verilog Compiler substitutes the text of the macro wherever it encounters a `<macro_name>. • Example: // define text marco `define WORD_SIZE 32 `define WORD_REG reg [31:0] module dummy (d, clk, myreg32); input [`WORD_SIZE - 1 : 0] d; // declare d[32-1:0] input clk; output [`WORD_SIZE - 1 : 0] myreg32; // declare myreg[32-1:0] `WORD_REG myreg32; // reg [31:0] myreg32; always @ ( posedge clk ) myreg32 = d; endmodule

  46. `include • Allows to include entire contents of a Verilog source file in another Verilog file during compilation. • Example: module clk_bk (clkin, clkout); input clkin; output clkout; assign clkout = ~clkin; endmodule `include “c:\test\clk_bk.v” // use file clk_bk.v `timescale 100 ns / 1 ns module dummy_test_bench; reg toggle; wire clk_out; clk_bk myclk (.clkin(toggle), .clkout(clk_out); initial toggle = 1’b0; always #5 toggle = ~toggle; endmodule File C:\test\clk_bk.v File C:\test\tstbch.v

  47. Conditional Compilation Directive • Conditional Compilation Directive: • `ifdef • `else • `endif • Use to specify that the particular portion of the source code be compiled only if a certain flag is set. • Example: `define TEXT `ifdef TEXT module test1 ……….endmodule `else module test2 ……….endmodule `endif

  48. Verilog Simulation

  49. pDS+ Viewlogic Verilog Simulation Flow Example Verilog Behavior Verilog Simulation Verilog Test Bench ViewLogic VCSi Verilog Simulator Verilog Synthesizer Gate Level Verilog Netlist Timing Simulation EDIF Verilog ispDS+ Fitter Verilog Test Bench .JED

  50. Simulation • Simulation Goals • Debug Verilog source • Verify performance of CPLD implementation • Two Stages of Simulation: • Register transfer level Verilog functional simulation • (Design Entry Level) • Gate-level Verilog timing Simulation • (Post-fitting Gate-level)

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