DKT 212/3 DIGITAL SYSTEM 2

1. DKT 212/3DIGITAL SYSTEM 2 CHAPTER 3 Counters

2. Overview • Introduction • Asynchronous Counter • Synchronous Counter • Design Synchronous Counter

3. Introduction • A counter – a group of flip-flops connected together to perform counting operations. • The number of flip-flops used and the way in which they are connected determine the number of states (modulus). • Two broad categories according to the way they are clocked: • Asynchronous counter • Synchronous counter

4. ASYNCHRONOUS COUNTER • Don’t have fixed time relationship with each other. • Triggering don’t occur at the same time. • Don’t have a common clock pulse • The clock input is always connected to LSB flip-flop A 2-bit asynchronous binary counter

5. The Timing Diagram • Main clock pulse only applied to FF0. • Clock for next FF, taken from previous complemented output (Q). • All inputs (J, K) are high (Vcc).

6. The Timing Diagram

7. 0 1 0 0 1 0 1 1 0 0 The Binary State Sequence

8. 3-bit asynchronous binary counter & timing diagram (1 cycle) Draw the output waveforms for Q0, Q1 and Q2

9. 3-bit asynchronous binary counter & timing diagram (1 cycle)

10. The Binary State Sequence for a 3-bit Binary Counter

11. Propagation delay • Asynchronous counters commonly referred as ripple counter • Effect of input clock pulse ‘ripples’ through the counter taking some time to reach the last flip-flop due to propagation delay.

12. 4-bit asynchronous binary counter & timing diagram

13. ASYNCHRONOUS DECADE COUNTER • The modulus of a counter is the number of unique states that the counter will sequence through. • The maximum possible number of states (max modulus) is 2n . Where n is the number of flip-flops. • Counter can also be designed to have a number of states in their sequence that is less than the maximum of 2n. The resulting sequence is called truncated sequence. • Counter with ten states are called decade counter. • To obtain a truncated sequence it is necessary to force the counter to recycle before going through all of its possible states.

14. decade counter • Decade counter with a count sequence of zero (0000) through nine (1001) is a BCD decade counter because its ten-state sequence produces the BCD code. • Required 4 flip-flop (3 insufficient because 23=8) • BCD decade counter must recycle back to 0000 state after 1001 state. • One way to make the counter recycle after the count of nine (1001) is to decode count ten (1010) with a NAND gate and connect the output of the NAND gate to clear (CLR) inputs of the flip-flop.

15. An asynchronously clocked decade counter

16. EXERCISE Example: Show how an asynchronous counter can be implemented having a modulus of twelve with a straight binary sequence from 0000 through 1011.

17. EXERCISE Solution: Q3 Q2 Q1 Q0 0 0 0 0 : : : : 1 0 1 1 1 1 0 0 Use NAND gate to reset flip-flop 2 and 3 to 0

18. SYNCHRONOUS COUNTER HIGH Q0 Q0Q1 Q0 Q1 Q2 J0 J1 J2 C C C K0 K1 K2 CLK In a synchronous counter all flip-flops are clocked together with a common clock pulse. Synchronous counters overcome the disadvantage of accumulated propagation delays, but generally they require more circuitry to control states changes. This 3-bit binary synchronous counter has the same count sequence as the 3-bit asynchronous counter shown previously 18

19. SYNCHRONOUS COUNTER OPERATION • A 2-bit synchronous binary counter

20. 0 1 0 0 1 0 0 1 1 0 The Binary State Sequence

21. A 3-bit synchronous binary counter

22. A 3-bit synchronous binary counter

23. The Binary State Sequence for a 3-bit Binary Counter Q2 change state when BOTH Q1 and Q0 are HIGH

24. A 4-bit synchronous binary counter and timing diagram Points where the AND gate outputs are HIGH are indicated by the shaded areas.

25. Synchronous BCD Decade Counter With some additional logic, a binary counter can be converted to a BCD synchronous decade counter. After reaching the count 1001, the counter recycles to 0000. This gate detects 1001, and causes FF3 to toggle on the next clock pulse. FF0 toggles on every clock pulse. Thus, the count starts over at 0000. 25

26. A 4-Bit Synchronous BCD Decade Counter

27. The Binary State Sequence for BCD Decade Counter

28. DESIGN OF SYNCHRONOUS COUNTERS • General clocked sequential circuit

29. Steps used in the design of sequential circuit • Specify the counter sequence and draw a state diagram • Derive a next-state table from the state diagram • Develop a transition table showing the flip-flop inputs required for each transition. The transition table is always the same for a given type of flip-flop • Transfer the J and K states from the transition table to Karnaugh maps. There is a Karnaugh map for each input of each flip-flop. • Group the Karnaugh map cells to generate and derive the logic expression for each flip-flop input. • Implement the expressions with combinational logic, and combine with the flip-flops to create the counter.

30. State diagram for a 3-bit Gray code counter

31. Next-state table for a 3-bit Gray code counter

32. Transition Table for a J-K flip-flop QN : present state QN+1: next state X: Don’t care

33. Karnaugh maps for present-state J and K inputs

34. Three-bit Gray code counter

35. EXAMPLE EXERCISE • Design a counter with the irregular binary count sequence as shown in the state diagram. Use J-K flip-flops.

36. EXAMPLE : TRANSITION TABLE

37. Transition Table for a J-K flip-flop

38. EXAMPLE : K-MAP

39. EXAMPLE : COUNTER CIRCUIT

40. Example 2: State diagram for a 3-bit up/down Gray code counter.

41. J and K maps. The UP/DOWN control input, Y, is treated as a fourth variable

42. 3-bit up/down Gray code counter