Lab 8 – Processing Time Improvement – Cache & branch

1. MPC8360Micro Controllers371-1-2403 Lab 8 –Processing Time Improvement – Cache & branch Fall , 2010

2. Objectives • Smart Branch Prediction • Caching

3. MPC 8360E General overview

4. Branch Prediction

5. Branch condition and Branch Prediction • BO – Branch Operand, the LSB of BO (y) use for Static Branch Prediction • BI – Bit condition • BD – Branch Destination (Target). • AA – Absolute Address • LK – Link Register Update 16 BO BI BD AA|LK

6. Caching

7. Cache Disks Memory Reg Faster and Expensive Caches Slower and Cheaper • Speed (Time to access) • Distance from the core • Technology – F.F vs. Disk • Management • Price ($) • Material • Design efforts • Failure / Damage recovery

8. Access Memory using Cache (DMA) Core Fatching E300Core CACHE 4 1 1 1 1 2 3 3 2 4 2 3 3 4 4 2 1 External Memory (DDR/HDD)

9. Cache • A small amount (normally less than 1MB) of high-speed memory residing on or close to the CPU. • Cache memory supplies the processor with the most frequently requested data and instructions. • Level 1 cache (primary cache) is the cache closest to the processor. • Level 2 cache (secondary cache) is the cache second closest to the processor.

10. Cache - why • Cache takes advantage of: • Spatial locality – most programs are highly sequential. • Data is usually structured, • The next instruction usually comes from he next memory location • Temporal locality - recently accessed items are likely to be accessed in the near future, let’s keep it in cache.

11. MPC8360 Cache Features • separate instruction and data caches. • 32Kbyte - instruction and data caches each. • Eight-way. • 32-byte Cache Line. • Cache locking, Entire cache locking or Way-locking. MPC 8360 E300Core I-CACHE CACHE 32K Bytes D-CACHE 32K Bytes

12. 0x100 0x00 0x120 0x20 0x40 0x140 0x160 0x60 0x80 0x180 0xA0 0x1A0 0x1C0 0xC0 0xE0 0x1E0 Mapping Policy - Direct Map 1 Way Associative Cache Size = 256Bytes Cache Line size = 32Bytes 256Byte Cache 0xAF 0x01 0x00 Line No’ 0 [0x00] Main Memory Line No’ 1[0x20] Line No’ 2 [0x40] Line No’ 3 [0x60] Line No’ 4[0x80] Line No’ 5[0xA0] Line No’ 6 [0xC0] Line No’ 7 [0xE0] Direct Map Each memory Line cached only by specific cache line, Usually, (memory address) mod (number of cache lines) gives cache address.

13. 0x00 0x100 0x120 0x20 0x40 0x140 0x160 0x60 0x80 0x180 0x1A0 0xA0 0x1C0 0xC0 0xE0 0x1E0 Mapping Policy - N Set Associative 2 Way Associative Cache Size = 256Bytes Cache Line size = 32Bytes 256Byte Cache 0xAF 0x01 0x00 Way - 1 Line No’ 0[0x00] Main Memory Line No’ 1 [0x20] Line No’ 2 [0x40] Line No’ 3[0x80] Way - 2 Line No’ 0 [0x00] Line No’ 1 [0x20] Line No’ 2 [0x40] Line No’ 3 [0x80] Set Associative Each memory addressed is covered by several blocks.

14. 0x100 0x00 0x120 0x20 0x140 0x40 0x160 0x60 0x80 0x180 0x1A0 0xA0 0xC0 0x1C0 0xE0 0x1E0 Mapping Policy – Full Associative Cache Size = 256Bytes Cache Line size = 32Bytes 0xAF 0x01 0x00 256Byte Cache Main Memory Way No’ 0 Way No’ 1 Way No’ 2 Way No’ 3 Way No’ 4 Way No’ 5 Way No’ 6 Way No’ 7 Full Associative Each cache way/line covers the all memory addresses .

15. Memory Address Mapping 0x100 0x00 0x20 0x120 0x140 0x40 0x160 0x60 0x80 0x180 0xA0 0x1A0 0xC0 0x1C0 0xE0 0x1E0 • How do we maps a 32bit address in memory to cache? • Cache line Offset - Cache Line contains 2k bytes • Way Offset - Index – • Each address (in memory) can be mapped to one or more locations in the cache. Depend on mapping policy. 0xAF 0x01 0x00 Main Memory Main Memory K bits for inline offset T bits for tagging I bits for Indexing 32 bit Address Cache line

16. MPC8360E Example T bits for tagging I bits for Indexing K bits for inline offset • Cache Size = 32K Bytes • 8-Way Set Associative • Cache Line size = 32 Bytes • K size[bits], • Cache Line = 32 Bytes -> 2k =32 , K=5, Adress[27-31] • I size[bits], • Way Size = 32K / 8 = 4K Bytes, 4K / 32 = 128 Lines -> • 2i = 128, I = 7, A[20-26] • T size[bits], • Address = 32 bit, T=32-7-5 = 20 bits, A[0-19] Tag 20 bits Index 7 bits Offset 5 bits Tag Index Offset

17. Who Cache Way Looks Like Status: the following four states indicate the status of each byte in the cache line: Index[0-127] Modified—The cache block is modified with respect to system memory; that is, data for this address is valid only in the cache and not in system memory. Exclusive—This byte holds valid data that is identical to the data at this address in system memory. No other cache has this data. Shared—Only available if HID2[MESISTATE] register bit is set. The byte is valid in the cache and in at least one other cache. This byte is always consistent with system memory. That is, the shared state is shared-unmodified; there is no sharedmodified state. Invalid—This cache byte does not hold valid data.

18. 8-Way Set Associative Example • Searching for address in cache T = 20 I = 7 K = 5 10010011110000010100 0011001 10000 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 8 Ways Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Tag Status Status W1 W1 W2 W2 W3 W3 W4 W4 W5 W5 W6 W6 W7 W7 W8 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Tag Status Status W1 W1 W2 W2 W3 W3 W4 W4 W5 W5 W6 W6 W7 W7 W8 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 W8 Tag Tag Status Status W1 W1 W2 W2 W3 W3 W4 W4 W5 W5 W6 W6 W7 W7 W8 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Tag Status Status W1 W1 W2 W2 W3 W3 W4 W4 W5 W5 W6 W6 W7 W7 W8 W8 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Tag Status Status W1 W1 W2 W2 W3 W3 W4 W4 W5 W5 W6 W6 W7 W7 W8 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Tag Status Status W1 W1 W2 W2 W3 W3 W4 W4 W5 W5 W6 W6 W7 W7 W8 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Index[0-127] Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Status W1 W2 W3 W4 W5 W6 W7 W8 Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Tag Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status Status W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W2 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W3 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W4 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W5 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W6 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W7 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8 W8

19. 8-Way Set Associative Example • Searching for address in cache T = 20 I = 7 K = 5 10010011110000010100 0011001 10000 Way [0], Tag[25] Way [1], Tag[25] Way [2], Tag[25] Way [3], Tag[25] Way [4], Tag[25] Way [5], Tag[25] Way [6], Tag[25] Way [7], Tag[25] Compare Result 0 0 1 0 0 0 0 0

20. HID0

21. HID0

22. HID0

23. HID0

24. HID0

25. HID0

26. HID2

27. HID2

28. HID2

29. dcbf

30. dcbi

31. dcbt

32. Program Structure In This Lab Session Initialization Phase Executing Phase Stop RTC Initiate system configurations Initiate GPRs Initiate Data Structures Reset the counter Enable the counter Capture the current counter value ……….. Exercise code ……… Disable the counter Capture the current counter value Calculate the difference between the captured values Start RTC Exercise

33. Polling&Timers The End