A 128Gb 3b/cell NAND Flash Design Using 20nm Planar-Cell Technology

1. A 128Gb 3b/cell NAND Flash Design Using 20nm Planar-Cell Technology Speaker : Naso Giovanni – Micron Flash Design Center Avezzano Italy ISSCC 2013 paper 12.5

2. Design team Micron Flash Design Center Italy : G. Naso, L. Botticchio, M. Castelli, C. Cerafogli, M. Cichocki, P. Conenna, A. D’Alessandro, L. De santis, D. Di Cicco, W. Di Francesco, M.L. Gallese, G. Gallo, M. Incarnati, C. Lattaro, A. Macerola, G. G. Marotta, V. Moschiano, D. Orlandi, F. Paolini, S. Perugini, L. Pilolli, P. Pistilli, G. Rizzo, F. Rori, M. Rossini, G. Santin, E. Sirizotti, A. Smaniotto, U. Siciliani, M. Tiburzi, T. Vali Micron Flash Design Center S. Jose (California) : M. Helm, R. Ghodsi Micron Flash Product/Process Engineering Boise (Idaho) : R. Meyer, A. Goda, B. Filipiak

3. Agenda Device features and architecture Planar NAND cell Ramped sensing for read and program verify Techniques to mitigate distributions shift and widening Typical single page uncycled time0 distributions Summary

4. Device features

5. Dynamic bits per cell configuration Number of bits per cell can be dynamically set by the user to 1, 2, 3 using a command. Program and read algo are optimized for the different bit per cell configurations to achieve maximum performance and margins. Pages addressing is automatically adjusted based on bits per cell configuration.

6. 3bits/cell throughput 2 bytes CK = data DDR = = 333 MB/s 6 nsec 8192 Bytes x 2 Sustain IN throughput = min(CK ; ) = 7.1 MB/s (dual plane) 2.3 msec 8192 Bytes x 2 Sustain OUT throughput = min(CK ; ) = 182 MB/s (dual plane) 90 usec

7. Sustainable throughput

8. Device architecture 128 Gbit at 3bits per cell Block selectors Plane 1 Plane 0 2 planes Page buffers Page buffers Core drive Control logic Core drive Data path LV pumps 146.5mm2 8 I/O Pads

9. String drivers Device photo Block selectors array Page buffers 2nd sensing Core drive LV analog Data path Core drive pumps controller pads

10. Plane organization 48 Mbit at 3bc block Plane 128 active WL per block 1368 blocks 384 pages at 3 bc Page buffers Bytes : 8192 regular + 1104 ECC

11. Previous 25nm WRAP technology C.G. IPD At 25nm and below, the WRAP technology does not allow to extend the Control Gate (C.G.) down to the Field Oxide. Floating Gates (F.G.) have an interface area that produces coupling. F.G. F.G. 22n Gate Oxide Field Oxide A.A.

12. Planar NAND Cell Control gate wrap-around design has a gap filling issue between floating gates as cell dimension further shrinks beyond 2X nm. HfO2 High-K inter-gate dielectric (IGD) is used to achieve the improved cell coupling factor which is decreased in planar floating gate cell. (HfO2 dielectric constant is about 6x greater than SiO2 dielectric constant). Planar technology has a reduced poly floating gate (FG) thickness to minimize cell-to-cell interference. Metal control gate (W tungsten with Ta/HfO2 interface) is used to engineer the work function preventing the erase saturation and balancing program and erase capability. It also allows to reduce the control gate resistivity which is an important factor when geometries are very small. Air gap isolation between word lines and bit lines is used to reduce cell cross-talk.

13. Planar NAND Cell High K dielectric Metal control gates Air gap for cell gates and BL Thin poly floating gate to mitigate FG-Fg interference wrap control gate planar

14. Planar NAND Cell airgap Between bit lines Between word lines

15. Ramped sensing concept WLDAC N bits counter WL DAC PB(0) PB(i) Page buffers PBDAC in out in out • Digital progressive values are generated by a counter and : • Fed into all page buffers (PB) • Converted into analog ramp by a digital to analog converter • (DAC) and applied to Word Line (WL) • Sensing /verify is performed at each ramp step

16. Ramped sensing to read threshold VT BL charged -> saout =0 BL discharged -> saout =1 BL SA saout string en WL en PB(i) PBDAC At each WL step the Bit Line (BL) is pre-charged and the current flowing into string is sensed by Sensamp (SA). If it is greater than a limit the digital value (PBDAC) is stored into each Page Buffer PB(i) and available at the output (out) and subsequent sensings are disabled. out

17. Ramped sensing for program verify BL charged -> saout =0 BL discharged -> saout =1 BL SA saout en inhibit L string WL match en PBDAC PB(i) diff BL is pre-charged Sense is enabled (en) if BL is discharged, then no inhibit if BL stay charged, then if match, then inhibit if no match, then no inhibit 1 2 in a b

18. Ramped sensing to evaluate distribution An embedded circuit allows to evaluate with a single ramp sensing operation how many cells have a specific threshold value VTx. After a complete ramp sensing operation is performed, each page buffer contains the VT value associated to its cells. These VT’s can be compared with a specific value VTx and counted saout_h saout_k PB(h) PB(k) PBDAC out_h out_k VTx diff diff L L count

19. Analog circuits for ramped sensing WL (Volt) Final value uniform compensation non uniform compensation Initial value nominal time Initial and final values of the ramp can be adjusted for temperature compensation. Uniform or non-uniform compensation is provided.

20. Analog circuits for ramped sensing • DAC_1 and DAC_2 to change • start/end points of the ramp • 2) DAC_0 to generate ramp steps Temperature compensation Band gap reference Register_2 DAC_2 resistor Final value Memory controller Memory core Register_1 DAC_1 Initial value WL Register_0 DAC_0

21. Techniques to mitigate distributions shift and widening • Pre compensation to mitigate FG-FG interference • in program operation • 2) Corrective read to mitigate FG-FG interference • in read operation • 3) Channel calibration to rebalance the read levels • by detecting the actual distributions separation. • This technique minimizes the Bit Error Rate (BER) • due to cycling/retention

22. Pre compensation to mitigate floating gate to floating gate interference Pre-compensation is a technique that can be applied during a program operation of a page and is performed internally to the chip. Its purpose is to mitigate the floating-gate to floating-gate interference on the actual page to be programmed coming from next surrounding pages in a stream. The external controller must provide the content of next pages to be programmed in order to account for possible aggressions on the actual page.

23. Pre compensation to mitigate floating gate to floating gate interference Pre compensation can take into account interference coming either from adjacent bit lines (odd page programmed after even page) or from adjacent word lines to be programmed next. Cells that will not be aggressed are programmed at their target value. Cells that will be aggressed are programmed at lower level in a way that they will be read at the target value after the aggression.

24. Pre compensation to mitigate floating gate to floating gate interference goal for target cells on WLn WLn+1 VT* VT WLn Cells that will not be aggressed bl0 bl2 bl1 bl3 even before aggressor program odd Cells that will be aggressed no FG-FG after aggressor program Page buffer Page buffer max FG-FG

25. Corrective read to mitigate floating gate to floating gate interference Corrective read is a feature having the purpose to perform data correction needed to compensate floating-gate to floating-gate interference after data (both victims and aggressors) have been programmed. Different flavors of corrective read are possible : aggression from upper WL, from single or both adjacent BLs. The corrective read features is activated by the external controller when error level is greater than the ECC capability and it is performed internally to the NAND.

26. Corrective read to mitigate floating gate to floating gate interference global distribution non aggressed cells aggressed cells VT t t t - 2nd read ramp on selected WL. - only not aggressed cells are enabled to be sensed - 3rd read with shifted ramp on selected WL - only aggressed cells are enabled to be sensed 1st read ramp on adjacent WL to detect the aggressors

27. Channel calibration to minimize BER • Purpose of Channel Calibration is to detect a read level • corresponding to the maximum separation (minimum overlap) • between two consecutive distributions. • It can mitigate overlaps due to different reasons : • Retention (down shift on upper distributions) • Cycling (distributions sigma widening : upper tail shift) • Temperature • Channel Calibration is performed upon user request when • the BER (Bit error Rate) level is considered too high for the • selected ECC technique.

28. Channel calibration to minimize BER • Channel Calibration is organized in two phases : • Optimum read level detection • Calibrated read using the optimized levels • The optimum read level detection can be performed • in two ways (they have different accuracy and different • performing penalties) : • 1) Single optimum read level detection (usually between two • consecutive higher distributions). In this case, all the • remaining read levels are rebalanced using a model • to account for optimum read levels of the lower distributions. • 2) Multiple optimum read level detection : the optimum value • is detected for all the read levels • Channel Calibration can be performed once per block and used • for all the pages of the block.

29. Channel calibration to minimize BER Start read ramp to detect VT of each cell count # cells associated to start VT value calibration search Threshold VT count # cells associated to lower VT values Actual valley Original valley (start value) Select VT corresponding to min count Perform a read level rebalance Time penalty for each optimum search : 40% of tread in case 500 bytes and 8 lower levels are used. calibrated read Perform a read operation using the new read levels

30. Typical single page uncycled time0 distributions sigma Threshold VT (arbitrary unit)

31. Press release

32. Summary • A 3bit/cell 128Gb NAND Flash at 20nm planar NAND • technology was presented. • The planar NAND technology allows to perform a shrink • in word line and bit line directions while reducing floating • gate to floating gate interference compared to the WRAP • technology. • Design techniques : • - Pre conditioning • - Read compensation • Channel calibration • allow to minimize the Bit Error Rate due to interference, • cycling, endurance.