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General Purpose FIFO on Virtex-6 FPGA ML605 board

General Purpose FIFO on Virtex-6 FPGA ML605 board. Students: Oleg Korenev Eugene Reznik Supervisor: Rolf Hilgendorf. Semester: spring 2012. Content. Project overview G oals Motivation Specifications Block Diagram Initial steps Possible solutions Workflow Timeline.

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General Purpose FIFO on Virtex-6 FPGA ML605 board

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  1. General Purpose FIFO on Virtex-6 FPGA ML605 board Students: Oleg Korenev Eugene Reznik Supervisor: Rolf Hilgendorf Semester: spring 2012

  2. Content • Project overview • Goals • Motivation • Specifications • Block Diagram • Initial steps • Possible solutions • Workflow • Timeline

  3. Project Overview • Design and implementation of General Purpose FIFO which allows usage of external memory(DDR III) as FIFO storage on Xilinx FPGA device • Design and implement generic IP core of FIFO • Design and implement GUI generator of IP core on PC • Create design which serves as sample application

  4. Our goals • Gain experience in hardware development (VHDL environment) • Explore and expertise FPGA work environment • Create design with configurable • word size • FIFO size • bandwidth • Achieve best performance • Minimize usage of FPGA resources • Make our world a better place

  5. Motivation • Why do we need big FIFO? • FPGA works relatively fast comparing to data transmission rate. So we need special storage to accumulate pre-processed and processed data. • Xilinx provides us with standard and relatively small FIFO (cores). • In case we need to process big chunks of data we will have to use big storage (FIFO). For example in signal processing.

  6. Specifications • Hardware • Xilinx Virtex-6 ML605 FPGA Evaluation Kit • DDR III memory • Ethernet interface • UART interface • PC with Ethernet interface • Software • ISE Design Suite Logic Edition Version 13.2 • PlanAhead Design and Analysis Tool   • ISIM/Modelsim

  7. Block Diagram Host FIFO region User Logic FIFO region User Logic FIFO area Virtex 6 Memory Controller AXI bus User Logic on FPGA FIFO Memory Arbiter Host FIFO controller User Logic FIFO controller CONTROLLER FIFO OUT FIFO IN FIFO IN FIFO OUT Host connection: ETHERNET/UART/PCIe Host PC

  8. Initial steps • External interface • Define FIFO interface • Define word size limitation and its connection to bandwidth • Choose external memory interface • Choose host data exchanging interface • Internal architecture • Define memory arbiter functionality • Define main controller functionality • Define host and user logic FIFO controllers functionality

  9. Possible solutions • Choose data exchanging interface • Ethernet • UART • PCIe • Choose external memory interface • AXI interface • Native interface • User interface • Max word size • 128 bits • Greater than 128 bits

  10. Workflow • Studying memory controller • Studying usage of Ethernet for communication with PC • Studying and generating standard FIFO with internal RAM • Implementation generalized FIFO controller • Implementing User Logic controller • Implementing Host FIFO controller • Implementing memory arbiter • Implementing main FIFO controller • Verification of design • Implementing GUI for generating FIFO IP core • Implementing sample design

  11. Timeline

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