Critical Path Test Generation in Asynchronous QDI Circuits

1. Amirkabir Univ. of Tech Computer eng. & IT Dept. Critical Path Test Generation in Asynchronous QDI Circuits Fahime Khoramnejad, Hossein Pedram Asynchronous Design Group

2. Outline QDI template based circuits Isolating a path Test Generation Finding the Critical Path in Data-Flow Graph Experimental results Summary and Future challenges Asynchronous Design Group

3. QDI template based circuits • One of most important asynchronous QDI circuit design methods is based on PCFB (Pre-Charged Full Buffer)/PCHB (Pre-Charged Half Buffer) templates. Output generation circuits. Input validity check circuit. Output validity check circuit. A sub circuit that generates the acknowledgment of inputs. A sub circuit that generates en signals

4. Persia • Persia, an asynchronous synthesis tool intended to provide automatic synthesis of QDI asynchronous circuits. • Persia synthesis tool uses a new method of asynchronous synthesis in which transformations are based on data dependencies in the source program. always begin `READ(Sel_In,S_In) if(S_In==1'b0) `READ(Data_In_0,D) else `READ(Data_In_1,D) `WRITE(Data_Out,D) end Asynchronous Design Group

5. Isolating a path • In order to isolate a path, all of the nodes in the path must be communicated through the channels which are in the path. • If a node in the path sends one token or more to a node(s) in another part of the graph, the spread of these tokens have to be prevented. As a result, the destination nodes convert to "Sink" nodes. • Sink node is a node that its output(s) remains neutral regardless of the tokens received during the test procedure. • A node in the path does not have to receive one token or more from the node(s) in another part of the graph during the test procedure. • These nodes being converted to "Source" nodes or an extra "Source-buffer" is inserted between them and the node in the path. • "Source" node or "Source-buffer" provides output(s) regardless of the input(s). Asynchronous Design Group

6. Input acknowledge generation Output valid generation Alloutack signal Sink node Asynchronous Design Group

7. output generation enable signal generation Source node Asynchronous Design Group

8. Convert to source No action Inserted source buffer Convert to sink Insert source buffer Insert source buffer Source node A node in path Convert to sink Convert to source Usual node in graph Asynchronous Design Group

9. Test Generation • QDI PCFB template-based asynchronous circuits have different behaviors in the presence of faults. Most of the time single stuck-at faults cause reactions that are enumerated as follows: • Dead lock • Token generation • Token consumption • Detecting faults that result in the generation or consumption of tokens is significant because the aforementioned faults bring about incorrect actions. • Data-flow testing studies whether a token, sent from a primary input to a primary output through a particular path, is received or dropped or some extra tokens are generated in the primary output due to a single stuck-at fault in the path. • By isolating all paths and applying data-flow testing, most of the faults in the circuit which result in token generation and token consumption are detected. • Using this method, causes an increase in power consumption, delay and area over head. • Finding the critical path in data-flow graph and isolating it not only causes a decrease in power consumption, delay and area over head but also leads to high fault coverage. Asynchronous Design Group

10. Test procedure Isolating the path Finding critical path AFE DSA Decomposition Data flow testing Technology Mapper Template Synthesizer Asynchronous Design Group

11. Finding the Critical Path in Data-Flow Graph • To find the critical path in a QDI circuit, the hardness of token's propagation is a suitable criterion. • A new definition of controllability in asynchronous QDI circuit is needed which is based on the propagation of tokens. • Both probability-based types of measures and SCOAP are used to determining the controllability of a data channel in asynchronous QDI circuits. • The encoding of data channels in asynchronous QDI circuits is done in dual-rail way. • Five numerical measures for each line L in data-flow graph have been considered: • Valid-controllability, CV(L) • Neutral-controllability, CN(L) • 1-valid-controllability, CV1(L) • 0-valid-controllability, CV0(L) • Logic depth, D(L) Asynchronous Design Group

12. Algorithm to find the critical path • The first step of this algorithm is to set the difficulty of controlling each primary input (PI): • CV(PI) is the probability of being valid: 2/3 • CN(PI) is the probability of being neutral: 1/3 • CV1(PI) is the probability of being one: 1/3 • CV0(PI) is the probability of being zero: 1/3 • In order to measure the controllability, asynchronous gates in output generation sub circuit and synchronous and asynchronous gates which somehow participate in calculating the conditions, are considered. • For all unconditional gates, CV(output) and CN(output) measures are computed as: • For all conditional gates, CV(output) and CN(output) measures are computed as: • In order to compute CV1(L) and CV0(L) in a gate, original formulas that are used in computing probability-based controllability in combinational gates, are applied. CV(output) = ∏ CV(inputs) CN(output) = 1- CV(output) CV(output) = ∏ CV(unconditional inputs) ×CV1(conditional input) CN(output) = 1- CV(output) Asynchronous Design Group

13. Experimental results Asynchronous Design Group

14. Summary and Future challenges • A new approach in test generation in asynchronous QDI circuits has been introduced which is called critical path test generation. • It uses statistical method to measure the controllability of data channels and determine the critical path in the data-flow graph of a QDI circuit. • Both SCOAP and probability based measurements have been used and by employing these specifications testability measurement has been proved. • The critical path is isolated and data-flow testing is used to detect the faults in the circuit. • This method can be an introduction of structural testing in asynchronous QDI circuits. Asynchronous Design Group

15. Thanks for your attention Asynchronous Design Group