Techniques for synthesizable ADC Design

1. School of Electrical Engineering and Computer Science COLLEGE OF ENGINEERING Stochastic A/D Conversion Synthesizing Analog Components Third-Order MASH • Create GDS (layout) and LEF (place-and-route) information • Link to synthesis tool alongside standard digital library • Explicitly place analog cells in Verilog description • Use place-and-route directives to guide layout • Use noise-shaping to compensate for device mismatch in synthesis • Integrator based on single-stage opamp with indirect common-mode feedback • Taped out in NSC 0.13μ and TSMC 65nm processes (measurement results to follow) • Rely on mismatch within components • With sufficient number of samples and well-understand probability distribution, can digitally correct non-linearity • Taped out in NSC 0.13μ (measurement results to follow) Techniques for synthesizable ADC Design 11b Pipeline using Ring Amplification • Ring amplifiers provide scalable solution in sub-micron processes • Full-bit redundancy between stages to account for place-and-route variations • Taped out in NSC 0.13μ and TSMC 65nm processes (measurement results to follow) • [1] Hershberg, B.; Weaver, S.; Sobue, K.; Takeuchi, S.; Hamashita, K.; Un-Ku Moon, "Ring amplifiers for switched-capacitor circuits," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International , vol., no., pp.460,462, 19-23 Feb. 2012 Biography • Allen Waters • B.S. Oregon State University, 2010 • Ph.D.student under Dr. Moon since 2010