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LHC Beam Synchronous Timing (BST) based on Timing, Trigger and Control (TTC) System.

LHC Beam Synchronous Timing (BST) based on Timing, Trigger and Control (TTC) System. BST Requirements. TTC Features. BST Transmission over TTC. Issues & Planning.

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LHC Beam Synchronous Timing (BST) based on Timing, Trigger and Control (TTC) System.

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  1. LHC Beam Synchronous Timing (BST)based on Timing, Trigger and Control (TTC) System. • BST Requirements • TTC Features • BST Transmission over TTC • Issues & Planning. BI day 2000 J.J. Savioz SL/BI/EM

  2. Transmission to all acquisition crates of:> Timing Signals: Bunch Clock (40MHz) Orbit Turn Clock (11KHz)> Beam Synchronous commands: Injection Warnings. Acquisition triggers. Real time settings. Post Mortem commands. LHC Beam Synchronous Timing based on T.T.C. System. • BST Requirements BI day 2000 J.J. Savioz SL/BI/EM

  3. LHC Beam Synchronous Timing based on T.T.C. System. • BST Requirements • Do we use an updated LEP BST or new system for LHC ? • Main differences between LEP and LHC Requirements: Number of bunches : 16  2808 Minimum bunch Spacing : 335  25 ns Maximum Overall Jitter : 50  5 ns Number of bytes: 8  32 Number of acquisition crates: 60  300 Acquisition crates location : US US + Tunnel ? > Reliability > Monitoring > Radiation hardness (Tunnel) After evaluation >> New system !! BI day 2000 J.J. Savioz SL/BI/EM

  4. LHC Beam Synchronous Timing based on T.T.C. System. • TTC Features • Timing, Trigger and Control Systems for LHC Detectors : RD 12 . Common Project financed entirely by the LHC experiment collaborations. • The TTC system provides the distribution of synchronous timing, trigger, and control signals, to electronics controllers relative to the LHC beam. • The TTC system uses single-mode fibre for the distribution of the machine timing signals from the PCR to the LHC experiment areas and radiation- tolerant multi-mode fibre for local TTC distribution at the experiments. • TTC signals are encoded at 160 MBaud = 4 * 40 MHz LHC Bunch clock. • More details available on web site: http://ttc.web.cern.ch/TTC/intro.html BI day 2000 J.J. Savioz SL/BI/EM

  5. LHC Beam Synchronous Timing based on T.T.C. System. • TTC Bloc Diagram LHC BunchClock ( 40 MHz ) Clock TTCVI 160 MBaud Encoder & Fibre Optic Transmitter Fibre Optic Receiver & TTCRx Clock VME Fibre Optic Distribution Network L1A A Channel L1 A Trig Ev. Cnt. Data B Channel 4 x FIFO Trig. Fifos SubAdd BI day 2000 J.J. Savioz SL/BI/EM

  6. LHC Beam Synchronous Timing based on T.T.C. System. • TTC Frame Description BI day 2000 J.J. Savioz SL/BI/EM

  7. LHC Beam Synchronous Timing based on T.T.C. System. • BST Transmission over TTC • Motivation: • Profit from RD12 investment. • Common system for Experiment area & accelerator. • Use EP / ESS facilities. • Price ~ 200FS/Channel (Without fibers) > > Save time & money ! • Implementation: ……. BI day 2000 J.J. Savioz SL/BI/EM

  8. LHC Beam Synchronous Timing based on T.T.C. System. • BST Transmission over TTC Global distribution Local distribution Message Transmitter MASTER CRATE TTC minicrate TTCtx TTCvi Encoder & Transmitter RF Signals To other TTC users M.M. Tree Coupler To all Acquisition Crate S.M. Tree Coupler TTCRx Acquisition CRATE SingleMode Fibers Message Receiver To all Buildings TTC for all users TTC for BST only New BST Design BI day 2000 J.J. Savioz SL/BI/EM

  9. LHC Beam Synchronous Timing based on T.T.C. System. • Message Transmission 40 MHz Orbit 11 KHz Machine Events Beam Parameters Process Request BST MESSAGE PROCESSOR TTCVI TTC Transmitter CRATE CH A Optical Distribution CH B FIFOs New BST Design TTC for BST only Global TTC BI day 2000 J.J. Savioz SL/BI/EM

  10. LHC Beam Synchronous Timing based on T.T.C. System. • Message Reception TTC Rx ASIC Optical Input Optical Input BI day 2000 J.J. Savioz SL/BI/EM

  11. LHC Beam Synchronous Timing based on T.T.C. System. • Message Reception Clock L1A trigger Out Data Out I2C Bunch Clock Local Turn Clock Coarse Delay Hardware Selection Hardware output Event Number Optical Input Local Bus Interface & Control logic IRQ & Sub Ad Out Local BUS Dual Ported Memory I2C Bus Interface TTC Rx New BST Design BI day 2000 J.J. Savioz SL/BI/EM

  12. LHC Beam Synchronous Timing based on T.T.C. System. • Issues & Planning. • Propose solution within the context of Tim W.G.  2000 • TTC Transmission test. “ • TTC vi / BST compatibility test. “ • Distribution in the Tunnel… ? • Rx Platform… (VME/PCI) ? • Final Specifications  Early 2001 • Hardware Prototype design  2001 • Radiation Hardness test (if necessary)  2002 • Software design  2002 • 1 st. batch manufacturing, test & installation  2003 • TI 8 & 1st LHC Octant Commissioning  2004 BI day 2000 J.J. Savioz SL/BI/EM

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