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L0 Calorimeter Trigger LHCb Bologna

L0 Calorimeter Trigger LHCb Bologna. U. Marconi INFN Sezione di Bologna. CSN1 Assisi, 22/9/04. Outline. Introduction Status of the Selection Boards Optical Transmitters Plans Requests. L0 Calorimeter Trigger. Detect a local high E T cluster in ECAL or HCAL 2x2 cells

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L0 Calorimeter Trigger LHCb Bologna

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  1. L0 Calorimeter Trigger LHCb Bologna U. Marconi INFN Sezione di Bologna CSN1 Assisi, 22/9/04

  2. Outline • Introduction • Status of the Selection Boards • Optical Transmitters • Plans • Requests

  3. L0 Calorimeter Trigger • Detect a local high ET cluster in ECAL or HCAL • 2x2 cells • From 8x8 cm2 (Inner ECAL) to 52x52 cm2 (Outer HCAL) • ECAL: 5952 cells 5952 possible clusters • Validation by PS/SPD (same geometry) to get electron and photon candidates • Combination to get π0 candidates. • HCAL : 1484 cells  1484 possible clusters • Add the ECAL ET in front if available Local Maximum Validation

  4. The Selection Crate • Data input @ 40 MHz • 28 electron clusters • 28 photon clusters • 2x28 neutral pion clusters (local, global) • 80 hadron clusters • 16 SPD hits partial sums • Data output to the L0DU @40MHz • Highest transverse energy clusters for each cluster type (5 highest) • Total transverse hadron energy (global trigger variable) • Total SPD hit multiplicity (global trigger variable) • Data output to the L1 trigger @1.1MHz • The entire set of the processed clusters

  5. Selection Board(Select 1st and 2nd highest) 12 channel optical transducer Fast Control TTCrq Deserialization Demu 2:1 Synchronization Ghosts removal to select the 2nd highest 10-ch 1-ch Tx Processing Unit 1200pins Deserialization Demu 2:1 Synchronization 1-ch Tx 8-ch 1-ch Tx Deserialization Demu 2:1 Synchronization 10-ch CCPC Glue Card ECS Bus adapter: PCI to JTAG and I2C

  6. Selection Board(Select 1st highest) 12 channel optical transducer Fast Control Highest and transverse energy sum TTCrq Deserialization Demu 2:1 Synchronization L0 10-ch To the L0DU 1-ch Tx Processing Unit Deserialization Demu 2:1 Synchronization 8-ch 1-ch Tx ECS Deserialization Demu 2:1 Synchronization CCPC Glue Card 10-ch L1 buffer 1-ch Tx L1 28 clusters of 32 bits to L1 in case of L0 accept

  7. Selection Board Test Setup Optical Fiber Links Single Channel Optical Transmitter Pattern Generator Selection Board Prototype

  8. BER measurements Pattern Generator Reference Pattern BERT Xilinx FPGA VME Control Fiber Optical 1.6 Gb/s Receiver boards Transmitter boards  80 meters  SDA 5000 Lecroy Crystal Oscillator 80MHz clock generator DG2040 Tektronix 40MHz Time of Measurements When no error are detected C.L. 90%

  9. Eye Diagram Technique • Oscilloscopio Lecroy SDA5000 Jitter sul clock

  10. Selection BoardInput Stage I N P U T Input stage: 1/3 of the final 9U board at the actual component density.

  11. Pattern Generator (BERT) Optical Transducer Single Channel Optical Tx Prototypes

  12. Test of the ECS (slow control) Test using the Linux OS Credit Card PC Genova test board Glue Card

  13. Optical Transmitters Mezzanine Boards Items: 112+20 boards

  14. Single Channel Optical Transmitter (top side) Control Status LED 40 mm Connectors 32 bits GOL VCSEL Control 40MHz Power Voltage-Optical Transducer Vertical Cavity Surface Emitting Laser, made by ULM Photonics type ULM850-05-TN-USMB0P. High speed up to 5 Gbps. SMA fibre connector. Operate on multimode fibre at wavelength of 850nm GOL Laser Diode SMA Connector Gigabit Optical Link, chip made by the CERN microelectronic group. It has been designed to be less sensitive to radiation effects

  15. Single Transmitter (bottom side) Dip switch to set the GOL I2C address SAMTEC High Speed Connectors 0.635mm Hi-Speed Header QTS and QSS series

  16. Multichannel Optical Transmitter I2C addresses Clock distributor 250 pin/connector 116 Optical Transducer HFBR772BH GOL Top side Bottom side

  17. Transmitter Test Board External Clock Pattern Generator TTCrq Filtered Clock QPLL 12 channels test platform 1 Channel test platform Single Channel Tx 32 bits @ 40 MHz

  18. Mechanical Specification Single channel optical link

  19. Mechanical Specification Multiple channels optical link

  20. Plans • December 2004: Test of the Optical Transmitters and test of the final prototype of the Selection Board • May-June 2005: Purchasing of the fundamental electronics components (GOLs, Laser Diodes, etc) and of the optical fibers and of the optical patch panel • December 2005: Building of the optical transmitters and the selection board

  21. Electronics Components

  22. 2005 requests for fundings

  23. The Selection Board Processing Unit Input Interface Output Interface Slow Control Fast Control

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