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L0 RICH Trigger Firmware Status

L0 RICH Trigger Firmware Status. Cristiano Santoni. Università degli studi di Perugia INFN - Sezione di Perugia. Collaboration meeting 18/12/2013. Tasks performed during the dry run. RICH trigger firmware integration in the TEL62 framework (thanks to Pisa for the support)

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L0 RICH Trigger Firmware Status

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  1. L0 RICH TriggerFirmware Status Cristiano Santoni • Università degli studi di Perugia • INFN - Sezione di Perugia • Collaboration meeting 18/12/2013

  2. Tasks performed during the dry run • RICH trigger firmware integration in the TEL62 • framework (thanks to Pisa for the support) • Simulation in Modelsim of the firmware (SL plus one PP) • using standard testbench available on SVN (used for the • simulation of the “generic” version of the firmware) • Test of the firmware loaded in a TEL62 pulsed by a patti

  3. RICH Trigger Firmware TO THE NEXT TEL62 PP SL TRIGGER GENERATOR HITS FROM TDCB PRIMITIVES MERGER HITS SORTING PP TO L0TP PP FINE TIME TO GLOBAL TIME TEL62 ID PP TO GPU PP CLUSTERS FINDER FROM PREVIOUS TEL62

  4. RICH Trigger Firmware: what we have TO THE NEXT TEL62 PP SL TRIGGER GENERATOR HITS FROM TDCB PRIMITIVES MERGER HITS SORTING PP TO L0TP PP FINE TIME TO GLOBAL TIME TEL62 ID PP TO GPU PP CLUSTERS FINDER FROM PREVIOUS TEL62

  5. RICH Trigger Firmware: what we miss TO THE NEXT TEL62 PP SL TRIGGER GENERATOR HITS FROM TDCB PRIMITIVES MERGER HITS SORTING PP TO L0TP PP FINE TIME TO GLOBAL TIME TEL62 ID PP TO GPU PP CLUSTERS FINDER FROM PREVIOUS TEL62

  6. Hit Sorting • Problems with timing violations in firmware: sorting algorithm need to be improved. • During tests a limit to the maximum number of hits in a 6.4 us frame was imposed (max 64 hits) to avoid timing problems, just to be sure that any error would not come from the sorting logic. • Timing problems solutions: • To sort data coming from different TDCs independently in order to • exploit parallelism • To simplify sorting logic • To add latency to the sorting logic

  7. Firmware Integration DONE: PP SL INPUT TDCB output PP-SL communication OUTPUT PP-SL communication MTP asssembler CONTROL Reset, clock, enable, … • TO DO: • Error notification • Logging • SOFTWARE: • TDSPY RICH version

  8. Resource utilization: PP CombinationalALUTs…………… 8% MemoryALUTs.………………… <1% Dedicatedlogic registers…………10% Total block memorybits…………<1%

  9. Resource utilization: SL CombinationalALUTs…………… 3% MemoryALUTs.………………… <1% Dedicatedlogicregisters………… 3% Total block memorybits………… 0%

  10. Firmware Simulation In the testbench, one SL plus one PP were instantiated while the others PP were simulated as not producing data (empty output fifo from the PP) A complete TEL62 with SL and 4 PPs will be simulated soon Firmware latency: Biggest latency contribution comes from sorting logic: 2N clock cycle (N number of hits in a 6.4 us frame) Additional latency is introduced also to find all the M hits in a cluster so another contribution of M clock cycle is introduced during this step Total latency: O(100 ns)

  11. Primitives Generation Current format (debug only): PRIMITIVE NUMBER MULTIPLICITY RESERVED FINETIME TIMESTAMP @ 25 ns 31 16 8 0 Official format: PRIMITIVE NUMBER PRIMITIVE ID RESERVED FINETIME TIMESTAMP @ 25 ns 31 16 8 0

  12. Conclusions The coreof the L0 RICH trigger firmwarewasdeveloped and tested: wewereabletoseeprimitivescoming out from the TEL62 with correct cluster averagetime and multiplicity Some modulesneedtobeimproved and missingfeaturewill beimplementedsoon A betterintegrationneedtobedonetouseall the featuresof the TEL62 framework The test phasewill continue in Perugia side by side with the developmentofnewfeaturesof the algorithm

  13. Spares

  14. Firmware test: primitives generation Tests were done using a patti to pulse the TEL62 with the RICH version of the firmware loaded The patti board was connected to some channels on which it periodically sends pulses From 1 to 64 channels were pulsed during tests The tests done with 1 to 32 channels gave correct results For 64 channels some problems raised due to a limitation on the maximum number of words that was set exactly to 64 (so having some words from noise, the multiplicity of the primitives generated by the signal was not 64 but 63 or 62).

  15. Firmware test: primitives generation by ROBERTO PIANDANI noise* validprimiteve timestamp 0x800 * 25 ns = 2048 * 25 ns = 51.2 us validprimiteve timestamp * due tounconnectedchannels

  16. Sorting Logic (1) SORTER 2 a s = MIN(a, b) b g = MAX(a, b) • Fullysynchronous • Low resourcesconsuption • Configurable in both data width and comparisonrange

  17. Sorting Logic (2) R S2 S2 S2 S2 S2 S2 INPUT LOAD R N toload + N tosort 2 N OUTPUT

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