Impact of Adaptive Voltage Scaling on Aging-Aware Signoff

1. Impact of Adaptive Voltage Scaling on Aging-Aware Signoff Tuck-Boon Chan, Wei-Ting Jonas Chan and Andrew B. Kahng VLSI CAD LABORATORY, UC San Diego

2. Outline • Introduction: BTI Aging and AVS • Signoff Problem • Observations and Proposed Heuristics • Experimental Results

3. Outline • Introduction: BTI Aging and AVS • Signoff Problem • Observations and Proposed Heuristics • Experimental Results

4. Intro: Bias Temperature Instability (BTI) |ΔVth| increases when device is on (stressed) |ΔVth| is partially recovered when device is off (relaxed) NBTI: PMOS PBTI:NMOS |Vgs| ON OFF ON OFF time Device aging (|ΔVth|) accumulates over time [VattikondaWC06]

5. Intro: Adaptive Voltage Scaling (AVS) • Accumulated BTI  higher |ΔVth|  slower circuit • AVS can be used to compensate for performance degradation Circuit performance Without AVS Circuit On-chip aging monitor With AVS target time Voltage regulator Circuit performance Vdd Closed-loop AVS time

6. Outline • Introduction: BTI Aging and AVS • Signoff Problem • Observations and Proposed Heuristics • Experimental Results

7. Problem: Signoff Corner Definition • Timing signoff: ensure circuit meets performance target under PVT variations & aging • Conventional signoff approach: • Analyze circuit timing at worst-case corners • Fix timing violations, re-run timing analysis • With BTI aging and AVS, what is the Vdd of the worst-cast corner for timing analysis? With BTI aging and AVS, the worst-case voltage corner is not obvious ? • Slowest circuit • Less aging • Slowest circuit • Worst-case aging • Faster circuit • Worst-case aging Too pessimistic ?

8. Derated Library Characterization & AVS • VBTI = Voltage for BTI aging estimation • Vlib = Voltage for circuit performance estimation (library characterization) • VBTIand Vlib are required in signoff • Good VBTI and Vlib selection should consider expected BTI + AVS • Aging and Vfinal are unknowns before circuit implementation Step 1 Step 2 Step 3 VBTI |Vt| Derated library Circuit implementation and signoff Vlib BTI degradation and AVS ? Vfinal circuit

9. Library Characterization for AVS Step 1 Step 2 Step 3 • Inconsistency among Vfinal, Vlib& VBTI • What is the design overhead when timing libraries are not properly characterized? • What are guidelines to define BTI- and AVS-aware signoff corners that guarantee timing correctness with littledesign overhead? • VBTI = Voltage for BTI aging estimation • Vlib = Voltage for circuit performance estimation (library characterization) • VBTIand Vlib are required in signoff • VBTI and Vlib depend on aging during AVS • Aging and Vfinal are unknowns before circuit implementation VBTI |Vt| Derated library Circuit implementation and signoff Vlib BTI degradation and AVS No obvious guideline to define VBTI and Vlib ? Vfinal circuit

10. Previous Works • There are many previous works on BTI + AVS • [Basoglo10] [Kumar11] [Mintarno11] … • No discussion of signoff for a circuit with BTI + AVS • Previous works assume a circuit is signed off with timing libraries without BTI degradation • Then analyze BTI + AVS effects on circuit timing • If circuit timing fails to meet requirements  design iteration + signoff  longer design time • An example of timing failure: AVS requires Vdd > maximum allowed voltage to compensate aging

11. Outline • Introduction: BTI Aging and AVS • Signoff Problem • Observations and Proposed Heuristics • Experimental Results

12. “Chicken and Egg” Loop • “Chicken and egg” loop in signoff • Derated library characterization is related to BTI + AVS • AVS affected by circuit implementation • Timing constraints, critical paths, etc. • Circuit is affected by library characterization Vfinal Circuit Vlib , VBTI Derated Libraries

13. Observation #1 • BTI is a “front-loaded” phenomenon • 50% BTI aging happens within the 1st year of circuit lifetime (total lifetime = 10 years) [Chan11] Vfinal • Most Vddincrement happens in early lifetime • Gap between Vdd and Vfinal reduces rapidly ≈70% Vdd increment in 1 year (remaining 30% over 9 years)

14. Heuristics #1 • Model BTI degradation with Vfinalthroughout lifetime • Aging of a flat Vfinal ≈ aging of an adaptive Vdd • But slightly pessimistic NBTI Vdd VBTI = Vlib ≈ Vfinal PBTI time

15. Vfinal Estimation • Problem: Vfinal is not available at early design stage (design has not been implemented) • Vfinal= Vdd @ end of life (to compensate BTI aging) • Gates along critical path • Timing slack at t = 0 • Circuit activity (BTI aging) • BTI aging depends on circuit activity • Assume DC or AC stress in derated library characterization ? ? ✔

16. Observation and Heuristic #2 • Observation #2: Vfinal is not sensitive to gate types • Heuristic #2: use average Vfinalof different gate types • Vfinal is a function of timing slack • Assume timing slack = 0 10mV

17. Proposed Library Characterization Flow • Heuristic #2: obtain Vheur by averaging Vfinal of different cells • Heuristic #1: use a “flat” Vheur to estimate BTI degradation Obtain Vheur (average of standard cells) Obtain derated library with VBTI = Vlib= Vheur Signoff circuit with derated library

18. Outline • Introduction: BTI Aging and AVS • Signoff Problem • Observations and Proposed Heuristics • Experimental Results

19. A Reference Signoff Flow • Basic idea: keep a consistent VBTI , VLIB and Vdd throughout circuit lifetime • Signoff flow: • Estimate aging at each time step • Update circuit timing and Vdd • Repeat until t = tfinal • Modify circuit and start over if Vfinal > maximum allowed voltage • No overhead in timing analysis, but very slow Many STA runs and library Vstep: AVS voltage step Vfinal: converged voltage

20. Technology and Benchmark Circuits • NANGATE library with 32nm PTM technology • Signoff for setup time violation • Temperature = 125C • Process corner = slow NMOS and PMOS • BTI degradation = {DC, AC} Supply voltages

21. Experiment Setup • Characterize different derated libraries • Evaluate impact of library characterization • Seven testcases • 1 : VBTI = Vlib= Vinit Ignore AVS • 2 : Most pessimistic deratedlibrary • 3 : VBTI = Vlib= Vmax Extreme corner for AVS • 4 : VBTI= Vfinal Do not overestimate aging but ignores AVS • 5 : No derated library (reference) • 6 : Proposed method with α=0 • 7 : Proposed method with α=0.03

22. Results for DC Scenario 1 : VBTI = Vlib= Vinit Ignore AVS 2 : Most pessimistic derated library 3 : VBTI = Vlib= Vmax Extreme corner for AVS 4 : Vbti = Vfinal Do not overestimate aging but ignores AVS 5 : No derated library (reference) 6 : Proposed method with α=0 7 : Proposed method with α=0.03 Good corners • Optimistic signoff corner • AVS increases supply voltage aggressively to compensate aging • Consume more power • May fail to meet timing if desired supply voltage > Vmax • Pessimistic signoff corner • Ovestimate aging and/or underestimate circuit performance • Large area overhead

23. Results for AC Scenario Good corners • Similar results as in the DC scenario • Design overheads due poorly characterized libraries (#1 to #4) are smaller compared to the DC scenario

24. Power vs. Area for All Designs • Overlay all data points (4 designs x {DC, AC}) Circuit signed off using our derated libraries Circuit signed off using other derated libraries “Knee” point for balanced area and power tradeoff

25. Conclusions • Voltage for aging estimation (VBTI), library characterization (Vlib) and operation (Vfinal) are inconsistent • Poorly-characterized libraries lead to circuit area or power overheads • We propose a flow to characterize a derated library • Heuristic #1: approximate Vlib = VBTI ≈ Vfinal • Heuristic #2: use replica circuits to estimate Vfinal • Circuits implemented with our derated libraries have similar area and power as those implemented from a reference flow

26. Future Works • A comprehensive aging- and AVS-aware library characterization including PVT corners • Consider hold time violation due to degradation in clock distribution network • Re-examine signoff corners with AVS • Do we still need to signoff at the worst-case corners?

27. Thank you!

28. Implementation of Reference Signoff Flow • Create new libraries for each time step is too slow • Alternative implementation • Pre-characterize libraries for different VBTI, Vlib • Interpolate power, leakage, and delay using the pre-characterized libraries Conventional STA

29. Interpolation Results • Compare values from actual libraries vs. interpolation • Interpolation errors are negligible

30. BTI Model • Use BTI model in [Vattikonda06] • Fitting parameters are characterized with published data in [Zafar06] NBTI [Zafar06]

31. BTI Aging and AVS • NBTI and PBTI degrade circuit performance over lifetime • Two variables of aging severity • Supply voltage: • Higher VDDspeeds up BTI aging • Activity: • Stressed: |Vth| of transistor increases when it is on • Relaxed: Part of the |Vth| increment is recovered when transistor is off • Degradation vs. Operation Modes Max VDD Degradation Max VDD Adaptive VDD Max VDD Adaptive VDD Adaptive VDD Signal probability Transistor stress time DC AC

32. Braking the Loop • VBTI= Vlib = Vfinalto avoid overly pessimistic or optimistic • Heuristic: estimate VBTI, Vlib with circuit replica Circuit Replica Vlib , VBTI Derated Libraries Vlib= VBTI ≈ Vfinal Vfinal Circuit