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FTK last year results

AMCHIP : The mini@sic has been produced and tested on the MiniLAMB ; AM05 designed: now under test; AM06 under design & simulation. The IP core from Silicon Creation provides successfully serialized I/O to the Amchip .

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FTK last year results

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  1. AMCHIP: The mini@sic has been produced and tested on the MiniLAMB; AM05 designed: now under test; AM06 under design & simulation. The IP core from Silicon Creation provides successfully serialized I/O to the Amchip. • BOARDS: FTK_IM and 2-D clustering: ongoingintegration. The motherboard AMBSLP is produced and tested with the MiniLamb. Tests of the Processing Unit (PU) (AMBSLP + AUX board) ongoing. • PHYSICS CASE/simulation: The FTK TDR and an internal note are produced. Plan for simulation is ongoing, fast simulation is needed. • Cooling tests: useful not final yet. • FTK PU • miniaturization • for Phase II • ongoing FTK last year results From VME 9U To ATCA

  2. AMchip06 Design Status Stabile (MI) – Crescioli (LPNHE) – Beretta (LNF) • One layout 14.6 mm x 10.8 mm; ready! to be checked with IMEC if the size is OK. MLM reticle (15x12 mm^2), dummy tape-out • Submission pilot run 9 wafers for 16 AMBs late autumn ~230 chips/wafer  ~2070 chips  ~1240 chips for a 60% yield > 19 boards. • Flip Chip package development longer than die production Needs info from Temperature simulation • Indicative lead times for an HFCBGA are: • HFC BGA design:              2-3weeks (after all info is available) • FC tooling:                           12 weeks (can vary dependent on material substrate) • Assembly:                           20 Work Days Saverio Citraro – University of Pisa & INFN TDAQ WEEK 2014 July 17 2014 - 2/15

  3. AMchip05 and its Test Stand Designers: Stabile (MI) – Crescioli (LPNHE) – Beretta (LNF) • ~100 prototypes arrived in Pisa July 10 Single chip (with ZIF) test board ready, but we recently discovered a bug ~15 days delay • LAMB PCB ready, assembled for July 20 we can start tests with LAMB Test setup: Beretta & Gatta (LNF), Rossi & Biesuz (PI) Saverio Citraro – University of Pisa & INFN TDAQ WEEK 2014 July 17 2014 - 2/15

  4. LAMBSLP Status S. Citraro (Pisa) • LAMB PCB readynext week • Totally compatible with AM chip05 and AM chip06 • Each Mezzanine holds 16 chips Saverio Citraro – University of Pisa & INFN TDAQ WEEK 2014 July 17 2014 - 2/15

  5. AMBSLP: Tests • Measures: • Jitter Analysis • BER • Eye diagram • Good results (Rossi, Luciano, Citraro, Piendibene – Pisa, Magalotti PG) Input Measure Output Measure

  6. Test Stand for the AMchip and LAMBa unit with PCI-express and ethernet (Rossi, Luciano, Citraro - Pisa)

  7. THE FTK_IM mezzanine (Sotiropoulou, Beretta, Annovi - LNF) and the INTEGRATION

  8. Cooling Tests Lanza (Pavia), Piendibene (Pisa) What we have understood and future plan: • Heat transfer from PCB-resistances to air is minimum and air is cold, PCB is hot. • Good air chilling and small area for ​​heat exchange • The board full of resistors does not emulates the AM boards behavior properly • In this week we are repeating the test with boards that are more similar with the final boards • We asked to IMEC also Temp Simulations to optimize the heat exchange capability of the AM chip06 Saverio Citraro – University of Pisa & INFN TDAQ WEEK 2014 July 17 2014 - 2/15

  9. PU evolution: integration of many FTK functions in a small form factor (C. Gentsos – FTK-IAPP) AMSiP Main goal is to integrate the FTK system in a more compact form First step will be to connect an AMChip, an FPGA and a RAM in a prototype board In the future the devices could be merged in a single package (AMSiP) That AMSiP will be the building block of the new processing unit, to be assembled in an ATCA board with new mezzanines

  10. RESPONSABILITA’ Management team Project Leader - A. Annovi (Frascati) Deputy Project Leader - M. Shochet (Chicago) Technical Coordinator - P. Giannetti (Pisa) Task Leaders FTK_IM - M. Beretta (Frascati) AMBoard- M. Piendibene (Pisa) LAMB- S. Citraro (Pisa) AMBoard and LAMB firmware – P. Luciano (Pisa) AM chip - A. Stabile (Milano), F. Crescioli (Parigi) System Integration and Software Global integration coordinator - L. Ancu (Geneve) Rack integration including power supplies, cooling, & safety - VME: Lanza (Pavia) + ATCA: Zhang (Argonne) Offline software coordinator - G. Volpi (Pisa) Monitoring software - T. Klimkovich (Heidelberg) Monitoring firmware - C. L. Sotiropoulou (Pisa, Thessaloniki) Database for FTK - S. Gadomski (Geneve) Online software - A. Negri (Pavia) Contact Persons: Interface to HLT and TDAQ operations - J. Zhang (Argonne), A. Negri (Pavia)

  11. Talks and papers 2013-2014 http://ftk-iapp.physics.auth.gr/Dissimination/talks.html • FTK Technical Design Report (2013). • RD 2013, Florence, Italy, July 2013 • "Variable resolution Associative Memory optimization and simulation for the ATLAS Fast Tracker project", presented by. C. Luongo, Slides, Paper. • "The Associative Memory system for the FTK processor at ATLAS", presented by. S. Citraro, Slides, Paper. • ICATPP 2013, Como, Italy, September 2013 • "The Associative Memory system for the FTK processor at ATLAS", presented by D. Magalotti, Slides, Paper. • "A Multi-Core FPGA-Based 2D-Clustering Algorithm for high-throughput data intensive applications", presented by C.-L. Sotiropoulou, Slides, Paper. • "Variable resolution Associative Memory for the Fast Tracker ATLAS upgrade", presented by A. AnnoviSlides. • IEEE NSS 2013, Seoul, Corea, October 2013 • "A Multi-Core FPGA-Based Clustering Algorithm for Real-Time Image Processing", presented by C.-L. Sotiropoulou Poster, Paper. • "The Associative Memory Boards for the FTK Processor at ATLAS", presented by A. Lanza Poster ppt, Paper. • "Next generation Associative Memory devices for the FTK tracking processor of the ATLAS experiment", presented by F. Crescioli Slides, Paper. • "Variable resolution pattern generation for the Associative Memory of the ATLAS FTK project", presented by A. Annovi Poster, • TWEPP 2013, Perugia, Italy, September 2013 • "Next generation Associative Memory devices for the FTK tracking processor of the ATLAS experiment", presented by M. Beretta Poster ATL-DAQ-SLIDE-2013-850 ppt, Paper. • "Design of a hardware track finder (Fast TracKer) for the ATLAS trigger", presented by G. Volpi Slides ppt, Paper. • RT 2014, Nara, Japan, May 2014 • "Associative Memory computing power and its simulation", presented by C. Luongo PosterSlides • "A Highly Parallel FPGA Implementation of a 2D-Clustering Algorithm for the ATLAS Fast Tracker (FTK) Processor", presented by N. Kimura SlidesPaper • TIPP 2014, Amsterdam, The Netherlands, June 2014 • "The Serial Link Processor for the Fast TracKer (FTK) at ATLAS", presented by P. LucianoSlidesPaper • "Future Evolution of the FTK Processing Unit", presented by C. Gentsos SlidesPaper • "A High Performance Multi-Core FPGA Implementation for 2D Pixel CLustering for the ATLAS Fast TracKer (FTK) Processor", presented by C.-L. Sotiropoulou SlidesPaper • WIT 2014, University of Pennsylvania, May 2014 • "A Parallel FPGA Implementation for Real-Time 2D Pixel Clustering for the ATLAS Fast Tracker (FTK) Processor", presented by S. Gkaitatzis SlidesPaper • "The Serial Link Processor for the Fast TracKer (FTK) at ATLAS", presented by V. LiberaliSlidesPaper

  12. RICHIESTE 2015 & SJ 2014 • Frascati: • 120 k€ (packaging dei chip prodotti, SJ AM06 testato e funzionante) • 100 k€ (test prod. AMchip06, SJ AM06 testato e funzionante) • Milano • 220 k€- 50 wafers di AMchip06 (SJ AMchip06 testato e funzionante) • Pisa • 30 k€ - AMBSLP & LAMB production (this year still development) • Pavia • 5 k€ - consumable for infrastructure work TOTAL: 475 k€, but 200 k€ should come from 2013: • 100 k€ SJ in Milano for AM06 tests • 100 k€ SJ in Frascati, not used because 100 k€ anticipated by DESY this year • Remaining 35 k€ in Frascati, problably will be requested next September this year

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