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COMP 4300 Computer Architecture Datapath

COMP 4300 Computer Architecture Datapath. Dr. Xiao Qin Auburn University http://www.eng.auburn.edu/~xqin xqin@auburn.edu. Fall, 2010. Datapath for Branch Instructions. beq rs, rt, offset. if (R[rs] == R[rt]) then PC ← PC+4 + s_extend(offset<<2). Datapath: More Detailed View.

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COMP 4300 Computer Architecture Datapath

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  1. COMP 4300 Computer ArchitectureDatapath Dr. Xiao Qin Auburn Universityhttp://www.eng.auburn.edu/~xqin xqin@auburn.edu Fall, 2010

  2. Datapath for Branch Instructions beq rs, rt, offset • if (R[rs] == R[rt]) then PC ← PC+4 + s_extend(offset<<2)

  3. Datapath: More Detailed View

  4. Simple Implementation • Include the functional units we need for each instruction

  5. RTL Code for MIPS add • Fetch Instruction = ROM[PC], PC=PC+4 • Read Operands ALUOp1 = Registers[rs-value], ALUOp2 = Registers[rt-value] • Add ALUOut = ALUOp1+ALUOp2 • Write Result Registers[rd-value] = ALUOut

  6. R1 P C R2 Inst. address R3 Add (control signals) Data Port#1 WriteRegister ReadRegister#1 Port#2 ReadRegister#2 ALU Datapath Components for MIPS add add R1, R2, R3

  7. R1 P C R2 Inst. address R3 add Data Port#1 WriteRegister CLK ReadRegister#1 Port#2 ReadRegister#2 ALU Datapath Connections for MIPS add add R1, R2, R3 Interconnections What is missing?

  8. R1 P C R2 Inst. address R3 add Data Port#1 WriteRegister ReadRegister#1 Port#2 ReadRegister#2 ALU Critical Path for MIPS add add R1, R2, R3 CLK Interconnections Critical path

  9. R1 P C R2 Inst. address -100 lw/sw Data Port#1 WriteRegister ReadRegister#1 Port#2 Address ReadRegister#2 16 32 SIGN-EXTEND DataOut ALU DataIn RAM Datapath Components for MIPS lw/sw lw R1, -100(R2) sw R1, -100(R2) 16 ROM Instruction Memory REGISTERS Data Memory

  10. R1 P C R2 Inst. address -100 lw Data Port#1 WriteRegister ReadRegister#1 Port#2 Address ReadRegister#2 16 32 SIGN-EXTEND DataOut DataIn RAM Connections for lw lw R1, -100(R2) ALU 16 ROM Instruction Memory REGISTERS Data Memory

  11. R1 (rt) P C R2 (rs) ALU Inst. address 16 (Imm) -100 ROM Instruction Memory REGISTERS lw Data Port#1 WriteRegister ReadRegister#1 Port#2 Address ReadRegister#2 16 32 SIGN-EXTEND DataOut DataIn RAM Data Memory Critical Path for lw lw R1, -100(R2)

  12. R1 P C R2 Inst. address -100 sw 16 32 SIGN-EXTEND Connections for sw sw R1, -100(R2) Data Port#1 WriteRegister ALU ReadRegister#1 16 Port#2 ROM ReadRegister#2 Instruction Memory REGISTERS Address DataOut DataIn RAM Data Memory

  13. R1 P C R2 Inst. address -100 sw 16 32 SIGN-EXTEND Critical Path for sw sw R1, -100(R2) Data Port#1 WriteRegister ALU ReadRegister#1 16 Port#2 ROM ReadRegister#2 Instruction Memory REGISTERS Address DataOut DataIn RAM Data Memory

  14. P C P C R1 R1 Inst. address Inst. address R2 R2 R3 -100 lw add lw R1, -100(R2) Data Data Port#1 Port#1 WriteRegister WriteRegister ALU ReadRegister#1 ReadRegister#1 16 Port#2 Port#2 SIGN-EXTEND Instruction Memory ReadRegister#2 ReadRegister#2 16 32 Address DataOut ALU DataIn RAM Data Memory Datapath Connections for MIPS add and lw add R1, R2, R3 CLK

  15. NEED MUX P C R1 ALU Inst. address 16 R2 Instruction Memory -100 lw Data Port#1 WriteRegister ReadRegister#1 Port#2 SIGN-EXTEND ReadRegister#2 16 32 Address DataOut DataIn RAM Data Memory Datapath Connections for MIPS add and lw

  16. NEED MUX P C R1 ALU Inst. address 16 R2 Instruction Memory -100 lw Data Port#1 WriteRegister ReadRegister#1 Port#2 SIGN-EXTEND ReadRegister#2 16 32 Address DataOut DataIn RAM Data Memory Combined Datapath: R-Type and Load/Store Instructions

  17. Combined Datapath: Executing an R-Type Instruction add rd,rs,rt

  18. Combined Datapath: Executing a load instruction lw rt,offset(rs)

  19. Combined Datapath: Executing a store instruction sw rt,offset(rs)

  20. Summary • Read Ch B.7-9

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