COMP 206: Computer Architecture and Implementation

Dec 29, 2012

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2. Outline. Course InformationLogisticsGradingSyllabusCourse OverviewTechnology TrendsMoore's LawThe CPU-Memory Gap. 3. Course Information (1). Time and PlaceMW 2:00-3:15pm, Sitterson Hall 011InstructorMontek Singhmontek@cs.unc.edu (not singh@cs!)SN 245, 962-1832Office hours: MW 3:1

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COMP 206: Computer Architecture and Implementation

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comp 206: computer architecture and implementation

2. Reading. Chapter 3: ILP and Its Dynamic ExploitationSection 3.1-3.3. 3. Dynamic Scheduling: Tomasulo's Algorithm. For IBM 360/91 (about three years after CDC 6600)Goal: High performance without special compilersDifferences between IBM 360 and CDC 6600 ISAIBM has only 2 register specifiers/instruction versus 3 in CDC 6600IBM has 4 FP registers versus 8 in CDC 6600Differences between Tomasulo Algorithm and ScoreboardControl and buffers distributed with Function Units versus centralized 9455

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2. Outline. Multiple-Issue ArchitecturesSuperscalar processorsVLIW (very long instruction word) processorsSchedulingStatically scheduled (using compiler techniques)Dynamically scheduled (using variants of Tomasulo's alg.)Reading: HP4, Sections 2.6-2.10. 3. Multiple Issue. Eliminating data a

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COMP 206: Computer Architecture and Implementation

2. Outline. IntroductionDRAM OrganizationChallengesBandwidthGranularityPerformanceReading: HP3 5.8 and 5.9. 3. Basics of DRAM Technology. DRAM (Dynamic RAM)Used mostly in main mem.Capacitor 1 transistor/bitNeed refresh every 4-8 ms5% of total timeRead is destructive (need for write-

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2. Ensembles of Disks. Key ideaUse collection of disk drives to improve characteristics of disk systems (storage capacity, bandwidth, etc.)Used in mainframes for a long timeRAIDRedundant Array of Inexpensive Disks (original 1988 acronym)Redundant Array of Independent Disks (redefined in 1992).

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COMP 206: Computer Architecture and Implementation

2. Outline. Quantitative Principles of Computer DesignAmdahl's law (make the common case fast)Performance MetricsMIPS, FLOPS, and all that?Examples. 3. Example 1 (see HP3 pp. 42-45 for more examples). Which change is more effective on a certain machine: speeding up 10-fold the floating point sq

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COMP 206: Computer Architecture and Implementation

2. Reading. Appendix A (Crosscutting Issues). 3. What is a Scoreboard?. A Scoreboard is a table maintained by the hardware:keeps track of instructions being fetched, issued, executed etc.keeps track of the resources (functional units and operands) they use/needkeeps track of which instructions mo

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COMP 206: Computer Architecture and Implementation

2. Outline. Cache CoherenceReading: HP3 Section 6.3

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COMP 206: Computer Architecture and Implementation. Montek Singh Wed, Nov 16, 2005 Topic: Main Memory (DRAM) Organization. Outline. Introduction DRAM Organization Challenges Bandwidth Granularity Performance Reading: HP3 5.8 and 5.9. Basics of DRAM Technology. DRAM (Dynamic RAM)

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