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Width Minimization In the Single-Electron Transistor Array Synthesis

Width Minimization In the Single-Electron Transistor Array Synthesis. Speaker: Chian Wei Liu Advisor: Dr. Chun-Yao Wang 2014/06/09. Outline. Introduction Motivation Problem formulation Width minimization approach Product term minimization

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Width Minimization In the Single-Electron Transistor Array Synthesis

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  1. Width Minimization In the Single-Electron Transistor Array Synthesis Speaker: Chian Wei Liu Advisor: Dr. Chun-Yao Wang 2014/06/09

  2. Outline • Introduction • Motivation • Problem formulation • Width minimization approach • Product term minimization • Branch-Then-Share aware variable reordering • SET array architecture relaxation • Branch-Then-Share product term reordering • Overall flow • Experimental result

  3. Introduction • Single-electron transistor (SET) • An SET has two receiving edges and one sending edge and a controller • It works like a switch that receives the electrons from its preceding devices through either its left or right edge and sends the electrons to its succeeding device depending on the control variable 1/0 0/1 = 0 = 1 = 0 = 1 0 0 1 1 1 0 1 0

  4. Introduction • Single-electron transistor array • A graph composed of hexagons • All sloping edges are configurable:short, open, active (high or low) • Active edges at the same row are controlled by a single variable active high active high a active low active low a short short current detector open open current detector b b (high,low) (high,low) (high,low) (high,low) 1 1

  5. Introduction • Fabric constraint • Two edges are configured simultaneously • The combination of left and right edges must be one of (high, low), (low, high), (short, short),and (open, open) in the SET array. • (high, low) and (low, high) cannot simultaneously appear in a row active high active low short open P0: 0110 P1: 010- P2: 11- - Constraint free Fabric constraint

  6. Outline • Introduction • Motivation • Problem formulation • Width minimization approach • Product term minimization • Branch-Then-Share aware variable reordering • SET array architecture relaxation • Branch-Then-Share product term reordering • Overall flow • Experimental result

  7. Motivation • The previous work focuses on reducing the number of hexagons in SET arrays. • The area of an SET array is the product of the bounded height and bounded width • The height is a constant that equals the number of inputs in the Boolean function. 1 1 -3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3

  8. Outline • Introduction • Motivation • Problem formulation • Width minimization approach • Product term minimization • Branch-Then-Share aware variable reordering • SET array architecture relaxation • Branch-Then-Share product term reordering • Overall flow • Experimental result

  9. Problem Formulation • Given: • A Boolean circuit and its linear threshold gate(LTG) network. • Objective: • Configuring the circuit into SET arrays result in the smaller width. Boolean circuit Our approach LTG network 1 -3 -2 -1 0 1 2 3

  10. Outline • Introduction • Motivation • Problem formulation • Width minimization approach • Product term minimization • Branch-Then-Share aware variable reordering • SET array architecture relaxation • Branch-Then-Share product term reordering • Overall flow • Experimental result

  11. Factors influencing the width • If the number of product terms to be mapped in a circuit is smaller, the width could be shortened • Reducing numbers of product terms P1: 101-- P2: 10011 P1: 10100 P2: 10101 P3: 10110 P4: 10111 P5: 10011 Width: 6 P1: 1010- P2: 10110 P3: 10-11 Width: 8

  12. Factors influencing the width • If node or edge sharings among product terms are more, the width could be shortened • Branch-Then-Share product terms • The pair of product terms will branch at one row (branch row) and merge in other row (share row), after the merging point the remaining variables should be the same value • Case: (01,10), (1-,01), (0-,10), (10,01), (10,0-), (01,1-) P1:000101 P2: 010001 P1:001001 P2: 010001 Width: 9 Width: 5

  13. Factors influencing the width • If the configuration in each row of SET array is relaxed to different types, more mapping opportunity can be exploited for width minimization. • Relaxing architecture to create more type of Branch-Then-Share Width: 6 Width: 3

  14. Factors influencing the width • P1: [1,0] P1: [1,-] P1: [1,0] P1: [0,1] P1: [0,-] P1: [0,1] • P2: [0,1] P2: [0,1] P2: [0,-] P2: [1,0] P2: [1,0]P2: [1,-] Twin type: P1 P2 : (low, high) : (low, high) : (high, low) : (high, low) • P1: [1,1] P1: [1,-] P1: [1,1] P1: [0,0] P1: [0,-]P1: [0,0] Invert type: • P2: [0,0] P2: [0,0] P2: [0,-] P2: [1,1] P2: [1,1] P2: [1,-] : (high, low) : (low, high) : (low, high) : (high, low) Twin type Invert type • P1: [1i,1] P2: [0i,0] • P1: [1t,0] P2: [0t,1] • [branch variable, share variable]

  15. Outline • Introduction • Motivation • Problem formulation • Width minimization approach • Product term minimization • Branch-Then-Share aware variable reordering • SET array architecture relaxation • Branch-Then-Share product term reordering • Overall flow • Experimental result

  16. Product term minimization • We try to compute disjoint product terms from a threshold network representation of a circuit • A threshold network is a network composed of linear threshold gate(LTG) The equation and symbol of a LTG

  17. Product term minimization • Assuming the weights are integers • Computing its disjoint product terms from the primary output (PO) towards the primary inputs (PIs)

  18. Computing product terms from an LTG • Computing the onset and offset of each LTG in the threshold network

  19. Computing product terms from LTG networks

  20. Swapping the symmetric inputs F a a a d n3 n3 e e n2 n1 n2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b b b 3 3 2 1 1 3 1 1 2 2 1 • Swapping these symmetric inputs so that each don’t care “–” corresponds to a larger fanin gate c c c e d d f f n2 n1 n1 n3 1 1 1 f F f

  21. Product term minimization • Product term computation from linear threshold networks • Product term computation from Boolean networks • Choosing the network with fewer product terms Boolean circuit BDD extraction selection A set of product terms LTG circuit LTG extraction

  22. Outline • Introduction • Motivation • Problem formulation • Width minimization approach • Product term minimization • Branch-Then-Share aware variable reordering • SET array architecture relaxation • Branch-Then-Share product term reordering • Overall flow • Experimental result

  23. BTS-aware variable reordering • Moving all share variables to the front (variable with ‘-’ is in the back-end) • Reordering the remaining variables according to the quantity of the bit value MAX: MAX: (a) (b) (c)

  24. BTS-aware variable reordering • Moving all share variables to the front (variable with ‘-’ is in the back-end) • Reordering the remaining variables according to the quantity of the bit value MAX: MAX: MAX: (d) (e) (f)

  25. BTS-aware variable reordering • Labeling the t and i of all the Branch-Then-Shares • Reordering variables according to the quantity of Branch-Then-Share it can provide a: b: c:e eee g g d: e: g g f: g: h: i: f f ->c ->e ->g ->i ->f ->h d ->b ->a Ordering (c) (a) (b)

  26. BTS-aware variable reordering Width: 9 Width: 8 1 1 1 (a) (b) (c)

  27. Branch-Then-Share identification • The conflicts among Branch-Then-Shares • Type conflict • The invert type and twin type occur in the same variable • Under the fabric constraint, one variable can only has one configuration so the invert type and twin type is impossible to occur in the same variable • Group conflict • There are more than one share groups in one product term • The pitfall invalid path may be conducted Type conflict Group conflict Conducted paths P1: 11011 P2: 10-11 P4: 10-00 Invalid: 11000

  28. Branch-then-Share identification • Checking type conflicts • Identifying the share type that provides more Branch-Then-Shares • Checking share conflicts • Identifying the share group that provides more Branch-Then-Shares (c) (a) (b)

  29. Outline • Introduction • Motivation • Problem formulation • Width minimization approach • Product term minimization • Branch-Then-Share aware variable reordering • SET array architecture relaxation • Branch-Then-Share product term reordering • Overall flow • Experimental result

  30. SET array architecture relaxation • The first row is always configured as (high,low) • When there is a Branch-then-share, determine the row structure to meet the Branch-and-share requirement • Other row structures are determined as the previous row structure if over half of variables changes their value.Otherwise, inverse the row structure

  31. Outline • Introduction • Motivation • Problem formulation • Width minimization approach • Product term minimization • Branch-Then-Share aware variable reordering • SET array architecture relaxation • Branch-Then-Share product term reordering • Overall flow • Experimental result

  32. BTS-aware product term reordering • Grouping product terms • Scanning all the product terms from the first variable until at least one of product terms have different bit values on the variable • Calculating the lowest location of Branch variable among the Branch-Then-Shares • Product term ordering determination • Determine the product term order by Branch-Then-Share location and group relation • Priority: Branch-Then-Share location > group relation

  33. BTS-aware product term reordering P1~P7 P1 1-0 1-1 P1~P5 P6, P7 1-0- 1-01 1-0-1 1-0-0 P2,P4,P5 P3 P1,P2,P4,P5 1-0-11 1-0-10 P4 P2,P5 Ordering : P4->P5->P1->P2->P3->P6->P7

  34. Outline • Introduction • Motivation • Problem formulation • Width minimization approach • Product term minimization • Branch-Then-Share aware variable reordering • SET array architecture relaxation • Branch-Then-Share product term reordering • Overall flow • Experimental result

  35. Overall flow An LTG circuit A Boolean circuit Product terms computation BDD-based method LTG-based method Architecture determination Fewer product terms Configure the first row architecture as (high, low). Configure the following row architectures according to the share type and quantity of the switchingamong the product terms. Variables reordering • Move all-shared variables to the front. • Reorder remaining variables according to the quantity of bit values in the variable among all the product terms. • Label all the Branch-then-Share structure. • Reorder variables according to the quantity of Branch-then-Share it can provide. Product terms reordering Grouping the product terms. Calculate the lowest location of branch variables among the Branch-then-Shares. Determine the ordering according to the group relationship and Branch-then-Share relationship. Branch-then-Share elimination Yes No type conflicts? Choose the share type that provide more Branch-Then-Share. Mapping process No Yes No group conflicts? Choose the share group that provide more Branch-Then-Share. SET arrays No

  36. Outline • Introduction • Motivation • Problem formulation • Width minimization approach • Product term minimization • Branch-Then-Share aware variable reordering • SET array architecture relaxation • Branch-Then-Share product term reordering • Overall flow • Experimental result

  37. Experimental result

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