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CR16CP LUS Presented By: Rana Jhanzaib Hamid

CR16CP LUS Presented By: Rana Jhanzaib Hamid. The CR16CPlus is a 16-bit Micro controller Instructions fetches and data transfers are performed via an industry-standard AMBA AHB interface.

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CR16CP LUS Presented By: Rana Jhanzaib Hamid

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  1. CR16CPLUS Presented By: Rana Jhanzaib Hamid

  2. The CR16CPlus is a 16-bit Micro controller Instructions fetches and data transfers are performed via an industry-standard AMBA AHB interface. A load-store unit decouples data transfers via AHB and allows the CPU to continue program execution while the data is being transferred from/to memory (in case there are no data dependencies). Powerful debug features are implemented by the CR16CPlus, such as support for up to 16 hardware breakpoints on code and/or data. Architecture

  3. BLOCK DIAGRAM

  4. Architecture Features 3-Stage Pipeline (Fetch - Decode – Execute) Variable Instruction Length (16, 32 or 48-bit Instruction Length) Two Operating Modes (User / Supervisor) Von-Neumann Bus Architecture, compliant to AMBATM 2.0 Load/Store Unit (LSU) 16 x 8 bit Hardware Multiplier (16/32 bit Result) 32-bit Barrell Shifter

  5. 1] General Purpose Registers R0 … R11 General-Purpose Registers for User R12, R13 Used by C-Compiler for Index Addressing Mode R14 (RA) Used by C-Compiler to store Function Return Address R15 (SP) User by C-Compiler as Supervisor Program Stack Pointer Register Set

  6. Register Set Diagram

  7. PC 24-bit Program Counter ISP Interrupt Stack Pointer USP User Mode Program Stack Pointer INTBASE Interrupt Dispatch Table Base Address CFG Processor Configuration Register PSR Processor Status Register C: Carry Bit L: Low Flag U: User Mode Flag (if set to 1, USP is used as Program Stack Pointer) F: General Condition Flag Z: Zero Flag N: Negative Flag E: Local Interrupt Enable Bit I: Global Interrupt Enable Bit 2] Dedicated Registers

  8. DSR Debug Status Register DCR Debug Control Register CAR0, CAR1 Compare Address Registers 0 & 1 3] Debug Registers

  9. The CR16CPlus can operate in two operating modes Supervisor Mode User Mode Operating Modes In supervisor mode, all processor resources are accessible from the running process. However, when in user mode, system resources and regions of memory can be protected

  10. Entered upon occurrence of any exception (trap or interrupt) Uses SP as Program Stack Pointer Intended to be used for the Execution of Kernel Routines of an Operating System (OS) After reset CR16CPlus starts in supervisor mode Supervisor Mode

  11. Can only be entered via Jump User instruction Uses USP as Program Stack Pointer Intended to be used for the Execution of tasks in OS-based applications User Mode

  12. After reset the CR16CP starts operating in Supervisor mode. Switching from Supervisor to User is performed by setting the U-bit in the PSR register. This can be accomplished by executing the JUSR (Jump User). Switching between Operating Modes

  13. 32-bit Address Range Address Space of 16MB of code memory (0 to 2^24-1) Address Space of 4GB of data memory (0 to 2^32-1) Data Addressing always byte-related (i.e., data can be addressed at byte-resolution) Supports Data Accesses on any Alignment Memory Organization

  14. Memory can be Logically Divided into the following regions: "Data", "Far Data" and "Far2 Data" distinguish data that is addressed in different ways depending on the location within address space. Address Space

  15. The CR16CPlus supports three types of stacks: Stacks

  16. ISP Register used as Interrupt Stack Pointer Interrupt stack used to save and restore the program state (PC, PSR) during exception handling PC and PSR are automatically pushed, by the hardware before entering an exception service procedure RETX instruction pops PC and PSR back from the interrupt stack Interrupt Stack

  17. SP Register (R15) used as Supervisor Program Stack Pointer Used by C Compiler to pass arguments to functions Used by C Compiler to store local variables PUSH, POP and POPRET instructions adjust the SP automatically Supervisor Program Stack

  18. USP Register used as User Program Stack Pointer (if PSR.U = 1) Used by C Compiler to pass arguments to functions Used by C Compiler to store local variables PUSH, POP and POPRET instructions adjust the SP automatically. User Program Stack

  19. Exception Handling Non-Maskable Interrupt (NMI) Maskable Interrupts (from up to 112 Sources, managed by Interrupt Controller Unit) Traps

  20. Traps Supervisor (SVC) Divide-by-Zero (DIZ) Flag (FLG) Software Breakpoint (BPT) Undefined Instruction (UND) Illegal Address (IAD) Debug (DBG) In-System-Emulation (ISE)

  21. The CR16CPlus uses a vectored exception scheme. Upon occurrence of an exception the CPU automatically reads out the start address of the exception service routine from a dispatch table, based on an exception-specific offset within the dispatch table (Vector Number). In case of a maskable Interrupt the vector number is read by the CPU from a dedicated, memory-mapped register of the Interrupt Controller. The dispatch table can be located anywhere within the available data address range. The base address of the dispatch table must be defined via the INTBASE register of the CR16CPuls. Dispatch Table

  22. Exception Processing Save PSR and PC on Interrupt Stack (ISP) Clear PSR.I bit to 0 => Interrupts disabled Clear PSR.U bit to 0 => Enter Supervisor Mode Read Vector Number from Interrupt Controller (if Maskable Interrupt) Read ISR Start Address from Dispatch Table Jump to ISR and execute. ISR terminated by RETX Instruction RETX restores PSR and PC from Interrupt Stack. (ISR = Interrupt Service Routine)

  23. Key Features of the CR16 Instruction Set: High Code-density due to variable Instruction Length (2/4/6 Byte Instructions) Multiply-Accumulate Instructions Efficient Bit-Manipulation Instructions in Register and Memory Load/Store Instruction for Single or Multiple Registers Instruction Set

  24. Addressing Modes Addressing Mode Register Relative Immediate Absolute Index Example ADDB R1, R2 BR *+10 MULW $4, R4 MOVB $0x55, R0 LOADB 4000, R6 LOADW [R12] 4 (R5,R4), R6

  25. Sample System Architecture An Instruction cache is place between the CR16CPlus core and the system AHB in order to speed-up program execution and to reduce the overall system bus utilization of the CPU. Lower-speed peripherals and I/O devices reside on the APB and are connected to the high-speed AHB via an AHB-APB Bridge.

  26. Min 4-pin JTAG (IEEE149.1) Communication with Tool Up to 16 hardware Breakpoints/Watchpoints Instruction Single-Step Non-intrusive measurement of execution time (clock cycles) between two Watchpoints Optional “Freeze” of Peripherals while CPU stopped in Debug Mode On-Chip Debug JTAG-based Debug-only

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