1 / 11

FPGA Implementation of Multicore AES 128/192/256

FPGA Implementation of Multicore AES 128/192/256. By: William Whitehouse. Objectives. Design an FPGA that is capable of AES encryption and decryption with 128, 192, and 256 bit keys. Optimize encryption/decryption throughput by implementing multiple cores

benecia-urban
Download Presentation

FPGA Implementation of Multicore AES 128/192/256

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. FPGA Implementation ofMulticore AES 128/192/256 By: William Whitehouse

  2. Objectives • Design an FPGA that is capable of AES encryption and decryption with 128, 192, and 256 bit keys. • Optimize encryption/decryption throughput by implementing multiple cores • Synthesize multi-core design and generate a simulated throughput

  3. AES Core Modules • Used AES Core Modules developed by Jerzy Gbur • Contains: • key_expansion.vhd – 128, 192, or 256 bit key expansion module • aes_enc.vhd – AES encryption module • aes_dec.vhd – AES decryption module

  4. Single AES Core Timing

  5. Single Core Wave

  6. Top Level Diagram

  7. Multi-Core Timing

  8. Multi-core Enc/Dec Wave

  9. AES Design Synthesis • Target FPGA: Xilinx Virtex 5 XC5VLX110

  10. Growth Opportunities • Add more Enc/Dec inputs and 11-core modules • Optimize the design for size • Allow the key to be different for each core • Use different AES Core

  11. Questions • Design is located at: http://code.google.com/p/multicore-aes-fpga/ • If you have any questions please email me at: wdwhiteh@iastate.edu

More Related