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Foundry-Portable, Mixed-Signal ASIC Design Center

Foundry-Portable, Mixed-Signal ASIC Design Center. A pplication of C ommercially M anufactured E lectronics. Problem Statement:. Traditional military sources of high-performance, mixed-signal ASIC technology are going away.

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Foundry-Portable, Mixed-Signal ASIC Design Center

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  1. Foundry-Portable, Mixed-Signal ASIC Design Center Application of Commercially Manufactured Electronics

  2. Problem Statement: • Traditional military sources of high-performance, mixed-signal ASIC technology are going away. • In the future, defense programs will need to use commercial sources for this technology, or do without. • Military business is not attractive to commercial ASIC foundries because they must divert scarce, specialized design resources from higher volume/profit, opportunities. • Commercial ASIC foundries tailor their processes and design rules toward applications that are typically used in less strenuous environments over shorter lifetimes. • Commercial ASIC foundries do not always characterize processes and provide models for the mil temp range.

  3. Program Goal: Establish the tools, knowledge and foundry agreements needed to provide U.S. defense programs with an affordable, portable & reliable access path to commercial mixed-signal ASIC foundries. Subgoal: Demonstrate this capability with a pathfinder IC design that is implemented in one or more commercial foundries & has been successfully ported between foundries

  4. Prolific - ProGenesis Automated Digital Library Migration Barcelona Design Optimized Cell Designs Boeing ACME-Related Productivity Enhancements NeoCAD/Ultra-Syn/NeoRF Boeing - Cell Miner Automated RF Design Optimization, Routing, and Layout - Boeing is Commercialization Demonstrator Cell Librarian Boeing Soft Cells Potential Commercialization Path Automated Sub-Cell Design & Layout Optimization Cadence - Virtuoso Custom Router NeoLinear - NeoCell Automated Analog Placement & Routing Automated Analog Routing

  5. Impact on Design Flow ACME ACME ACME Deliver ACME Cadence Flow Shown ACME

  6. NeoCad Program

  7. Prolific SPICE Netlist ProGenesis GDSII ProGen Detailed Place & Route, Compaction, Post-Process ProGenerate Device Generators Global Place & Route ProMigrate Digital Cell Library GDSII GDSII Digital Cell Library Migration - Prolific Migrates up to 400 cells in 8 - 12 hr

  8. Cadence Virtuoso Custom Router (VCR) • Automatic Cell-Level Routing • Interactive Placement SPICE Netlist &Placement VCR GDSII • Can match signal characteristics • Coax and Differential Routing • Can control crosstalk • Critical Net Pre-routing Foundry Technology Files

  9. NeoLinear Tools • Device Sizing Optimization • In Development • Auto Analog Place & Route • RFP Issued NeoLinear and Cadence have a new agreement allowing Cadence to Distribute and Support NeoCell SPICE Netlist NeoCircuit NeoCell GDSII Sized Netlist • Any Topology • Can match signal characteristics • Coax and Differential Routing • Can control crosstalk • Preserves Placement Symmetry User’s Test Bench Foundry Technology Files

  10. Barcelona Design • Optimizer is designed specifically for each topology offered • Tool runs at Barcelona Design Facility - no maintenance required • Quick simulation • All parameters available without test bench design Web-Based Interface • Web Pages • Process Selection • Topology Selection • Requirements • Simulation Results Sized Netlist and GDSII Optimizer Foundry Technology Files Topology Library

  11. Barcelona Design Costs • A design run is defined as a “Design Click” • Op Amp trades may involve multiple Design Clicks • An annual $20k subscription allows unlimited Design Clicks Typical manual design cost: $8400

  12. Boeing Cell Librarian and Design Synthesis Tools CellMiner Librarian Organizes library & promotes re-use BiasNet Soft Cell Unit Resistor Sizing & Placement Optimization • CapNet Soft Cell in progress • HV XSTR Soft Cell planned • WSU current mirror soft cell • Pursuing commercialization

  13. Pathfinder Concept AMI C5N 0.5 um, 2 poly, 3 metal Barcelona Design & Low-Offset Amp Characterization Cells Bump Bond Corner Test Structures - Six Corners Georgia Tech. Reliability Test Structures 250 mil x 250 mil HV Transistor Array - Demonstrates Migration Avenue from HV to LV Processes ACME A Reliability Test Structures F-22 PSM Channel Optional Scribe Line to Enhance Test Options BiasNet & CapNet Soft Cell Test Structures - Validates Sensitivity-Weighted Optimization

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