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DØ PMG Agenda June 27, 2001

DØ PMG Agenda June 27, 2001. Overview (Weerts) DAQ & Trigger Detector status (experts are here). If time permits:. Financial status. DØ Detector Summary. Status: June 27, 2001. CFT, CPS, FPS. AFE 8. AFE 12. L1 Trig. VLPC. VLPC. DAQ. Fiber tracker readout front end system status.

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DØ PMG Agenda June 27, 2001

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  1. DØ PMG AgendaJune 27, 2001 • Overview (Weerts) • DAQ & Trigger Detector status (experts are here) If time permits: • Financial status

  2. DØ Detector Summary Status: June 27, 2001

  3. CFT, CPS, FPS AFE 8 AFE 12 L1 Trig VLPC VLPC DAQ Fiber tracker readout front end system status * Increase # AFE8; decrease #AFE12 to minimally readout CFT, CPS. Delay FPS (AFE12).

  4. CFT/CPS readout & trigger overview

  5. Fiber Tracker; Electronics • Tracking Electronics • Analog Front End (AFE) boards • 146 PCB’s exist (two kinds LHB, RHB) • 73 RHBs stuffed • First 7 at DØ & testing • Water problems….. • Remaining 66 RHB being shipped • 73 LHB expected ~ mid July • Test stands at DAB and SiDet ready; crews ready to go • Start on first 7 boards • More AFE boards • 54 more AFE PCB’s made for CPS and complete CFT stereo • Preparing order to stuff • 40 more AFE with modified VLPC bias distribution for FPS; working on layout changes Only one kind of AFE, no more AFE8 & AFE12 Schedule for AFE: Complete during September shutdown; may request shorter access before that to install first 16.

  6. Fiber Tracker; Electronics • Tracking Electronics; cont’d • Mixer Boards ( need 20) • CD has 2 prototypes ready • One person working on this ( great job!) • Expect completion in ~8 weeks • Digital Front End (DFE) boards; need 40 • Have 20 installed • Other 20 exist, but need testing • Collector & Broadcasters • Technical/production problems with “double wide” daughter cards; BGA mounting problems critical CFT readout & triggering will not be complete before end of September shutdown Start with parts of system earlier

  7. The SIFT chip replacement ( what is needed to run at 132nsec) History: • 8 Multichip modules (MCM) on each AFE board • Each MCM contains SIFT (trigger pick off) and SVX2 chips ( precision readout) • The current MCM does not work at 132nsec.  need to replace Solution: Use components of SVX4 ( being developed at FNAL: pipeline & preamp) Use commercial FADC New package will replace whole MCM (no more SIFT or SVX2) This work has started. This may become tight if Tevatron really moves change over to 132nsec to summer of next year.

  8. Trigger/DAQ Status Level 1 status Trigger systems: framework, LØ ( lum), tracker, calorimeter, muon

  9. Trigger/DAQ Status L2 overview S L I C L2MUO MUO L1MUO z-vertices (?) SMT STT refit tracks Matching of objects L2CFT CFT L1CFT L2 Global axial CPS stereo (u,v) L2CPS L2FPS Event-wide trigger decision FPS L1FPS CAL L1CAL L2CAL Bring up first preprocessor ( no inputs) with readout to L3 next week. Critical path are: L2 Alpha’s. Have 9 “working” ones Fabricating 12 more

  10. L2Alpha status L2 cont’d • Two integration challenges: • MBT-MBus-Alpha Broadcast/DMA • it required layout + firmware modifications • Alpha-MBus-Alpha Program I/O • it seems to be a firmware issue; not fixed yet • CDF noticed another integration challenge; addressed in the current design • MBus arbitration signals are PECL and sensitive to noise glitches from CDF’s MBus I/O cards • new design supports both TTL (new) and PECL (default for DØ) levels • Assembly of 12 additional boards has started • PCB’s delivered yesterday from Paragon but have to fix; the solder mask didn’t overlap the pads on the BGA’s; delay of ~10 days • ADCO ready to assembly the 2 prototype boards • all chips baked according to IPC standards • expect boards around the week of July 23 • Failed to repair a broken CIA board by replacing the CIA with a socket • too many broken vias after rework and bowed around the CIA (consistent with previous experience) give up • The L2beta project prototype design started

  11. o o o o o o o o o o o o L3 DAQ-FILTERING SCHEMATIC Infrastructure from Run I Front-End Digitizing Crates (2 of 16 groups) Data collection paths (16 total, ea. 48 Mbyte/s) VBD VBD o o o Readout Controller (VRC) (1 of 8) VRC VBD VBD o o o Primary Fiber Path (8 total, each 100 Mbyte/s) Ethernet Trigger data SB SB Event Tag Generator (ETG) SB Event tag path SB o o o Segment Controllers (SB) Processor Nodes (4 groups of 16) Filter Nodes (Linux) Switch

  12. Trigger/DAQ Status L3 status in words Original goals: • Built on existing infrastructure (VBD, data cables) for VME readout • Custom fast data path using PC’s with custom hardware in PCI slots  design SIB’s to do this. • Use NT operating system on all PC’s in this system • System and software implemented, but on emulators • Input rate into L3 of order 4-8 Hz (!!) • Only limited #filters ported to NT • NT support very difficult ( impossible) Status: Very slow development over last few months Oversight & planning committees (CD) • Bring up a system with >100Hz • System (1000 Hz) by September 2001 Decsions now: • Add a Linux based farm for filtering; only develop under Unix/Linux; no NT development. Orders out; strong team; will work by September • Make onlySIB1 work in VRC; gives ~100Hz. Problems: noise on chipsets used; now fixed and working on integration with software; however no clear delivery date) • Developing alternate solutions downstream of VRC with CD and start discussion with experts

  13. Summary • All detectors hooked up and taking data in one form or another. • Data rate is very slow; have to improve • Things remaining for completion: • Fiber Tracker (AFE) first boards here; now test • Fiber Tracker mixer boards and DFE’s are also on critical path. • Trigger • Level 1 coming up • Level 2 still large uncertainties in L2Alphas; starting to commission parts of system • Level 3 is critical system. Developing alternate solutions as back up. Being looked at by experts.

  14. L1MU Card Status

  15. Level 3 overview SB SB Node Node Node Node Node Node Node Node SB SB Data Collection Paths (8 * 2 * 48 MB/s) VBD VBD VBD o o o VRC Primary Fiber Paths (8 * 100 MB/s) (1 of 8) VBD VBD VBD o o o Level 1,2 Trigger Info ETG o o o event tag path o o o o o o o o o L3 data distribution to Level 3 farm

  16. Alternate solution for Level 3 Assumes that the SIB1 i.e. VRC will work.

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