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Lecture 14

Lecture 14. Flip-Flops Section 5.5-5.6. Schedule. Please bring a functional random number generator to class on Thursday (3/27). Outline. Review of Flip-flops D flip-flops JK flip-flops T flip-flop Analysis of a simple sequential circuit. Symbol of D Flip-Flops. r eset and preset.

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Lecture 14

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  1. Lecture 14 Flip-Flops Section 5.5-5.6

  2. Schedule Please bring a functional random number generator to class on Thursday (3/27).

  3. Outline • Review of Flip-flops • D flip-flops • JK flip-flops • T flip-flop • Analysis of a simple sequential circuit

  4. Symbol of D Flip-Flops

  5. reset and preset • When power is first turned on, the state of the flip-flops is unknown. • Reset is used to initialize the output to a 0. • Preset is used to initialize the output to a 1.

  6. D Flip-flop with reset Typo in the book. Should be 1 instead.

  7. JK Flip-Flops D=JQ’+K’Q Positive edge D flip-flop The next value of D is determined by JQ’+K’Q. At the rising edge of D Flip-flop, Q is updated with the value of D.

  8. D=JQ’+K’Q • J=1,K=1→D=Q’ • J=0, K=0→D=Q • J=0, K=1→D=0 • J=1, K=0→D=Q’+Q=1

  9. Verilog Implementation

  10. T Flip-Flop

  11. T Flip-Flop from a D Flip-Flop DT rst DT=TQ’+T’Q If T=1, D=Q’ If T=0, D=Q. Q is updated with D at the next rising edge.

  12. Verilog Implementation of a T-FF DT rst

  13. Example of a Sequential Circuit D flip-flops

  14. Example of a Sequential Circuit D flip-flops

  15. Construction of a State Table Example: Start with A=0, B=0, x=0. A(next)=0 B(next)=0 Y(next)=0

  16. Construction of a State Table Example: Start with A=0, B=0, x=0. A(next)=0 B(next)=0 Y(next)=0

  17. What are A(next), B(next) and y(next) given that A=1, B=1 and X=1? D flip-flops

  18. Alternate State Table

  19. Alternate State Table

  20. State Diagram Each circle is a state When x=1, y=0.

  21. State Diagram Each circle is a state When x=0, y=1.

  22. Detects 0 in the bit stream of data Output is a 0 as long as input is a 1. The first 0 after a string of 1s transfers the circuit back to 00.

  23. Detects 0 in the bit stream of data Output is a 0 as long as input is a 1. The first 0 after a string of 1s transfers the circuit back to 00.

  24. Detects 0 in the bit stream of data Output is a 0 as long as input is a 1. The first 0 after a string of 1s transfers the circuit back to 00.

  25. Summary

  26. Model a Clocked Sequential Circuit with Verilog Use parameter to represent each state Form the next state from x (the input) and the current state Form the output fork.....join construction S0 S2 S1 S3

  27. Parameter S0 S2 S1 S3 Define states with parameter

  28. Update States S0 S2 If reset is 0, set state to S0. If reset is 1, update state with next_state. S1 S3

  29. Syntax for always

  30. Implement the States Using State Diagram S0 S2 S1 S3 The always statement will be initiated if there is a change in state or x_in

  31. fork....join Statements within fork….join block execute in parallel, so the time delays are relative to t=0.

  32. Valid Mealy Output S0 S2 S1 S3

  33. Mealy Glitches Glitiches occur because x changes before the next rising clock edge S0 S2 S1 S3

  34. Synthesizable Verilog • http://www.youtube.com/watch?v=YTId6cpTEFM

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