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CS 6020 - Chapter 3 (3A and 10.2.2) – Part 5 of 5

CS 6020 - Chapter 3 (3A and 10.2.2) – Part 5 of 5. Dr. Clincy Professor of CS. Maybe some time will be remaining after tonight’s class for final project teams to meet. Dr. Clincy. Lecture. Slide 1. Previous State or Output. Previous State or Output. Circuit. Flip Flops.

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CS 6020 - Chapter 3 (3A and 10.2.2) – Part 5 of 5

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  1. CS 6020 - Chapter 3 (3A and 10.2.2) – Part 5 of 5 Dr. Clincy Professor of CS Maybe some time will be remaining after tonight’s class for final project teams to meet Dr. Clincy Lecture Slide 1

  2. Previous State or Output Previous State or Output Circuit Flip Flops Current State or Output New Input Circuit New Input Current State or Output Sequential Circuits Vs Combinational Circuits Sequential Logic Current State or output of the device is affected by the previous states Combinatorial or Combinational Logic Current State or output of the device is only affected by the current inputs Lecture

  3. Clock - Sequential Circuits • State changes are controlled by clocks (clock ticks). • Circuits can change state on the rising edge, falling edge, or when the clock pulse reaches its highest voltage – edge triggered. • Level-triggered circuits change state when the clock voltage reaches its highest or lowest level. Lecture

  4. Previous State or Output Previous State or Output Circuit Flip Flops Current State or Output New Input Flip Flops - Sequential Circuits Notice how the output feeds the input Think of: Given R=0 and Qa=0, what can this be ? • S and R stand for set and reset respectively • constructed from a pair of cross-coupled NOR gates • the stored bit is present on the output marked Qa • If S and R inputs are both low, maintains the Qa and Qb in constant state, • If S (Set) is pulsed high while R is held low, then the Qa output is forced high,and stays high even after S returns low; • if R (Reset) is pulsed high while S is held low, then the Qa output is forced low, and stays low even after R returns low. Lecture

  5. Gated SR Latch or Flip Flop • The time at which the latch is SET or RESET is controlled by a CLOCK input • Called Gated SR Latch Lecture

  6. Gated D Latch • Inputs S and R are derived from a single input D • Clock pulse controls when the output is triggered • Samples the D input at the time the clock is HIGH and stores that info until the next clock pulse During the time the clock is high, the input changed,causing the output to change – this is the problem Lecture

  7. Potential Problem • Thus far, the assumption has been the inputs S and R (or D) not changing while CLK is HIGH • What would happen if S, R and/or D changed ? The output would change immediately • This could be a problem • To fix this (next ppt) During the time the clock is high, the input changed,causing the output to change – this is the problem Lecture

  8. Two Flip Flop Use To Fix Clock Issue FF1 FF2 Q Q m s D D Q D Q Q Clock Clk Q Clk Q Q Use 2 D flip flops – the FF2 clock is set to zero – therefore, if there was a change in FF1 input, D, it wouldn’t effect the FF2 Q value – FF2 holds the value (a) Circuit Clock D Q m Q = Q s (b) Timing diagram Clock’s negative edge causes change • If D changes while FF1 CLK is HIGH, Qm changes immediately - Qs stays the same because FF2 CLK=0 • Once the CLK goes LOW, FF2 reacts because its CLK=1 – so it thens reflects D Q D The arrow only symbolizes “positive edge” clock - the arrow with the NOT symbolizes “negative edge” clock Q (c) Graphical symbol Lecture

  9. T Flip Flop T Flip Flops are good for counters – changes its state every clock cycle, if the input, T, is 1 • Positive-edge triggered flip flop • Since the previous state of Q was 0, it complements it to 1 Lecture

  10. JK Flip Flop Combines the behavior of the SR and T flip flops • First three entries are the same behavior as the SR Latch (when CLK=1) • Usually the state S=R=1 undefined – for the JK Flip Flop, for J=K=1, next state is the complement of the present state Can store data like a D Flip Flop or can tie J & K inputs together and use to build counters (like a T flip flop) Lecture

  11. Registers and Shift Registers A Flip Flop can store ONE bit – in being able to handle a WORD, you will need a number of flip flops (32, 64, etc) arranged in a common structure called a REGISTER. • All flip flops are synchronized by a common clock • Data written into (loaded) flip flops at the same time • Data is read from all flip flops at the same time F F F F 1 2 3 4 In Out D Q D Q D Q D Q Clock Q Q Q Q A simple shift register. • Want the ability to rotate and shift the data • Clock pulse will cause the contents of F1, F2, F3 and F4 to shift right (serially) • To do a rotation, simply connect OUT to IN Lecture

  12. Registers and Shift Registers • Can load either serially or in parallel • When clock pulse occurs, • Serial shift takes place if Shift’/Load=0 or • if Shift’/Load=1, parallel load is performed Lecture

  13. Counters • 3-stage or 3-bit counter constructed using T Flip Flops • With T Flip Flips, when input T=1, the flip flop toggles – changes state for each successive clock pulse • Initially all set to 0 • When clock pulse, Q0=1, therefore Q’=0 disabling Q1 and Q1 disables Q2 (have 1,0,0) • For the 2nd clock pulse, Q0=0, therefore Q’=1, causing Q1=1 and therefore Q’=0 disabling Q2 (have 0,1,0) • For the 3rd clock pulse, Q0=1, therefore Q’=0 disabling Q2 and therefore disabling Q3 (have 1,1,0) • Etc…. LSB 000 001 010 011 100 101 110 111 Hmmm Lecture Called a Ripple Counter

  14. Sequential Logic Current State or output of the device is affected by the previous states Previous State or Output Previous State or Output Circuit Flip Flops Current State or Output New Input Combinatorial or Combinational Logic Current State or output of the device is only affected by the current inputs Circuit New Input Current State or Output Recall Examples: Decoders Multiplexers Examples: Shift Registers Counters Lecture

  15. x = 0 ¤ z = 0 S0 S1 x = 1 ¤ z = 0 x = 1 ¤ z = 0 x = 0 ¤ z = 0 x = 0 ¤ z = 0 x = 1 ¤ z = 1 x = 1 ¤ z = 0 S3 S2 x = 0 ¤ z = 1 State diagram of a mod-4 up/down counter that detects the count of 2. Sequential Circuit – State Diagram If x=0, count up, If x=1, count down Interested when 2 is realized – z=1 when reach 2, else z=0 If at 0 and x=0, count up to 1 (and z=0) If at 0 and x=1, count down to 3 (and z=0) State diagram describes the functional behavior without any reference to implementation Lecture

  16. x = 0 ¤ z = 0 S0 S1 x = 1 ¤ z = 0 x = 1 ¤ z = 0 x = 0 ¤ z = 0 x = 0 ¤ z = 0 x = 1 ¤ z = 1 x = 1 ¤ z = 0 S3 S2 x = 0 ¤ z = 1 State diagram of a mod-4 up/down counter that detects the count of 2. Sequential Circuit – State Table Can represent the info in the state diagram in a state table Lecture

  17. Sequential Circuit – Equation Inputs – y2,y1,x Outputs –Y2, Y1 Lecture

  18. Sequential Circuit – Circuit Design D Flip Flops used to store values of the two state variables between clock pulses Output from Flip Flops is the present-state of the variables Input, D, of the Flip Flops is the next-state of the variables Lecture

  19. Finite State Machine Model The example we just implemented is an example of a “Finite State Machine” - is a model or abstraction of behavior composed of a finite number of states, transitions between those states, and actions Lecture

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