Students: Nir Sheffi Evgeny Bogokovsky Instructor: Isaschar Walter Winter 2004

1. Students: Nir Sheffi Evgeny Bogokovsky Instructor: Isaschar Walter Winter 2004 טכניון – מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Memory Controller for a Satellite Midterm Presentation

2. Problems In Space • Short time “Bit Flips” • Permanent malfunction –“Latch Ups” Memory is especially vulnerable to these kind of failures ! Goal : Building a reliable Memory Controller ! Memory Controller for Satellite

3. Block Diagram of Conventional Memory System PowerPC405 ( CPU ) PLB Memory Controller SDRAM Memory Memory Controller for Satellite

4. Block Diagram of a Memory System using TMR with 3 Conventional Controllers Memory Controller 2 SDRAM Memory EDAC EDAC Memory Controller 3 PowerPC405 ( CPU ) PLB EDAC SDRAM Memory Memory Controller 1 TMR Unit SDRAM Memory Memory Controller for Satellite

5. Basic System Information • Operating frequency : 100 MHz • Max BW : 400 MB/Sec (or 133 MB/sec due to hardware constraints). • Refresh cycle: 64msec • 32 bits of data bus • 32 bits of address. Memory Controller for Satellite

6. Read PLB Transaction Memory Controller for Satellite

7. Write PLB Transaction Memory Controller for Satellite

8. SDRAM Block Diagram Memory Controller for Satellite

9. 8M X 16 SDRAM Memory Controller for Satellite

10. SDRAM Read Transaction Memory Controller for Satellite

11. SDRAM Write Transaction Memory Controller for Satellite

12. Block Diagram of a Memory System with Corruption Unit SDRAM Memory EDAC Memory Controller Corruption Unit PowerPC405 ( CPU ) PLB SDRAM Memory SDRAM Memory Memory Controller for Satellite

13. Completed Tasks • Study the Virtex-II Pro component design. • Study the PPC405 Processor core • Study the VHDL development environment and VHDL. • Writing a tester hardware of the LED’s – from VHDL design through synthesis, and place&route using Xillinx EDK. Done Done Done Done Midterm Memory Controller for Satellite

14. First Semester Goals • Writing a tester software for the Power PC (activation of LCD). • Writing a tester software with use of UART capabilities (Telnet). • Building up a standard computer system and writing an application to test its memory. • Implementing an hardware which corrupts the memory. • First draft of a reliable memory system. 1 week 1 week 1 week 1 week Final Memory Controller for Satellite

15. Second Semester Goals • Study the probability model of error in a memory system in space. • Review different options of possible memory controllers and EDAC in means of optimal BER. • Implementation of the optimal (if possible) memory controller and EDAC unit. • Debug. • System integration of the memory system in a complete computer system. Memory Controller for Satellite