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BOOLEAN ALGEBRA

BOOLEAN ALGEBRA. Saras M. Srivastava PGT (Computer Science) Kendriya Vidyalaya , IISc Bangalore – 560 012. What is logic ?. Any logical things have only two state either true or false. Example : Is 12 – 10 = 2 Yes Is India post populated country in the world? No.

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BOOLEAN ALGEBRA

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  1. BOOLEAN ALGEBRA Saras M. Srivastava PGT (Computer Science) KendriyaVidyalaya, IISc Bangalore – 560 012

  2. What is logic ? Any logical things have only two state either true or false. Example : Is 12 – 10 = 2 Yes Is India post populated country in the world? No Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  3. BINARY VALUED QUANTITIES • Binary Decision : • THE DECISION which results into eitherYES /TRUEORNO/FALSE • Tautology : • If the result of any logical statement or expression is alwaysTRUE or 1 • Fallacy : • If the result is alwaysFALSE or 0 Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  4. BINARY VALUED QUANTITIES • Binary Decision : • THE DECISION which results into eitherYES /TRUEORNO/FALSE • Tautology : • If the result of any logical statement or expression is alwaysTRUE or 1 • Fallacy : • If the result is alwaysFALSE or 0 Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  5. LOGICAL OPERATIONS • Logic operations • NOT (Complement)- Changes TRUE to FALSE, 1 to 0, high to low. • AND —“A AND B” is true if A and B are individually true (A•B, AB, A.B) • OR—“A OR B” is true if either A or B is true (or both are true) (A+B, A.B). Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  6. Evaluation of Boolean Expression using truth table Prepare truth table X’Y’ + X’Y XY’(Z+YZ’) + Z’ Prove using truth table (X + Y)’ = X’Y’ X + XY = X Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  7. LOGIC GATES

  8. Gate is an electronic circuit which operates on one or more signals to produce an output signal. Basically there are three type of Logic Gate. What is logic Gate ? Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  9. TRUTH TABLES Truth table Represents all the possible values of logical variables / statements along with all the possible results of the given combination of values. Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  10. A A’ Symbol Input Output Inverter (NOT Gate) Truth Table This Gate operates on single variable and operation performed by NOT operator called complementation. Thus A means complement of A’. Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  11. A A.B B AND GATE: The AND Gate have two or more than two input signals and produce an out put signal. Two input AND Gate Truth Table If both inputs signals are 1 (i.e. high) then the output will also be 1 (i.e. high). Otherwise, the output will be 0 (i.e. low). Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  12. A A+B B OR Gate: The OR Gate have two or more than two input signals and produce an out put signal. If either of the two input signals are 1 (high), or both of them are 1 (high), the output will be 1 (high). Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  13. Universal Gates NAND and NOR Gate are known as Universal Gate because any Boolean function can be constructed using only NAND or only NOR gates.

  14. The NAND Gate: The NAND (Not AND) Gate has two or more input signal but only one output signal. If All the inputs are 1 (i.e. high), then the output l is 0 (i.e. low) A Y B The NAND gate is a combination of an AND gate followed by an inverter (not Gate). It is compliment of AND Gate. Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  15. NAND Gates into Other Gates:- A Y A Y B A Y B We can create other gates with the help of NAND Gate. NOT Gate AND Gate Saras M. Srivastava PGT CS, KV IISc, Bangalore 12 OR Gate

  16. A Y B NOR Gate : The NOR (Not OR) Gate has two or more input signal but only one output signal. If All the inputs are 0 (i.e. low), then the output signal is 1 (i.e. high) Truth Table for NOR Gate The NOR gate is a combination of an OR gate followed by an inverter (not Gate). It is compliment of OR Gate.

  17. A Y=AB’+A’B B XOR Gate (Exclusive OR Gate):-We use XOR Gate for parity check.XOR Gate produces output 1 for only those inputs combinations that have odd number of 1’s. # Odd number of 1’s produce output 1. • Two input XOR Gate # A B= AB’+A’B + Truth Table for XOR Gate :

  18. XNOR Gate (Exclusive NOR Gate):-We use XNOR Gate for parity check. XNOR Gate produces output 1 for only those inputs combinations that have even number of 1’s. # Even number of 1’s and 0’s produce output 1. • Truth Table for Two Input XNOR Gate • A B=AB+A’B’

  19. Laws & Theorems of Boolean Algebra

  20. Boolean Algebra • A Boolean algebra is defined as a closed algebraic system containing a set K (two or more) elements and two operators,  and +. • Operators + and  are similar to + and x. • Useful for identifying and minimizing circuit functionality • Identity elements • a + 0 = a • a  1 = a • 0 is the identity element for the + operation. • 1 is the identity element for the  operation. Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  21. Duality • The principle of duality says that if an expression is valid in Boolean algebra, the dual of that expression is also valid. • To form the dual of an expression, replace all + operators with  operators, all  operators with + operators, all ones with zeros, and all zeros with ones. • Form the dual of the expression a + (b  c) = (a + b)  (a + c) • Following the replacement rules… a  (b + c) = a  b + a  c Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  22. Commutativity and Associativity • The Commutative Property: For every a and b in K, • a + b = b + a • a  b = b  a • The Associative Property: For every a, b, and c in K, • a + (b + c) = (a + b) + c • a  (b  c) = (a  b)  c Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  23. Distributivity and Complements • The Distributive Property: For every a, b, and c in K, • a  ( b + c ) = ( a  b ) + ( a  c ) • a + ( b  c ) = ( a + b )  ( a + c ) • The Existence of the Complement: For every a in K there exists a unique element called a’ (complement of a) such that, • a + a’ = 1 • a  a’ = 0 Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  24. Involution This theorem states: a’’ = a Taking the double inverse of a value will give the initial value. Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  25. Absorption This theorem states: a + ab = a a(a+b) = a To prove the first half of this theorem: a + ab = a . 1 + ab = a (1 + b) = a (b + 1) = a (1) a + ab = a Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  26. DeMorgan’s Theorem A key theorem in simplifying Boolean algebra expression is DeMorgan’s Theorem. It states: (a + b)’ = a’b’ and (ab)’ = a’ + b’ Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  27. G 0 0 0 1 0 0 1 1 Truth Table to Boolean Expression Any Boolean Expression can be represented in sum of products form! x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 xyz + xyz’ + x’yz • Converting a truth table to an expression • Each row with output of 1 becomes a product term • Sum product terms (SOP) together. Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  28. x x x x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 G 0 0 0 1 0 0 1 1 G x x x x x x x z y G = xyz + xyz’ + x’yz Equivalent Circuit Representations Number of 1’s in truth table output column equals AND terms for Sum-of-Products (SOP) Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  29. Minterms and Maxterms Each variable in a Boolean expression is a literal Boolean variables can appear in normal (x) or complement form (x’) Each AND combination of terms is a minterm Each OR combination of terms is a maxterm Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  30. Minterms and Maxterms: Example Minterms x y z Minterm 0 0 0 x’y’z’ m0 0 0 1 x’y’z m1 … 1 0 0 xy’z’ m4 … 1 1 1 xyz m7 : Maxterms x y z Maxterm 0 0 0 x+y+z M0 0 0 1 x+y+z’ M1 … 1 0 0 x’+y+z M4 … 1 1 1 x’+y’+z’ M7 Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  31. x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 G 0 0 0 1 0 0 1 1 Functions with Minterms G = xyz + xyz’ + x’yz G = m7 + m6 + m3 = Σ(3, 6, 7) Minterm number same as row position in truth table (starting from top from 0) Shorthand way to represent functions Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  32. G 0 0 0 1 0 0 1 1 G’ 1 1 1 0 1 1 0 0 Complementing Functions x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 G = xyz + xyz’ + x’yz G’ = (xyz + xyz’ + x’yz)’ Can we find a simpler representation? Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  33. x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 G 0 0 0 1 0 0 1 1 Conversion Between Canonical Forms G = xyz + xyz’ + x’yz G = m7 + m6 + m3 = Σ(3, 6, 7) G = M0M1M2M4M5 = Π(0,1,2,4,5) G = (x+y+z)(x+y+z’)(x+y’+z)(x’+y+z)(x’+y+z’) Easy to convert between minterm and maxterm representations For maxterm representation, select rows with 0’s Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  34. B 0 1 A 0 0 1 F=AB +AB +AB  1 1 1 A B F C 0 0 0 0 0 0 1 1 BC 0 1 0 1 00 01 11 10 0 1 1 0 A 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 + KarnaughMaps • Three variable maps. F=AB’C’ +AB C +ABC +ABC  + A’B’C + A’BC’ A Karnaugh map is a graphical tool for assisting in the general simplification procedure. Two variable maps. Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  35. Rules for K-Maps We can reduce functions by circling 1’s in the K-map Each circle represents minterm reduction Following circling, we get minimized and-or form. Rules to consider Every cell containing a 1 must be included at least once. The largest possible “power of 2 rectangle” must be enclosed. The 1’s must be enclosed in the smallest possible number of rectangles. Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  36. B 0 1 A 0 0 1 1 1 1 BC 00 01 11 10 A 0 0 1 0 1 1 1 1 1 1 KarnaughMaps F=AB +AB +AB  F=A+B • Three variable maps. F=A+B C +BC  F=AB’C’ +AB C +ABC +ABC  + A’B’C + A’BC’ Two variable maps. Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  37. G(A,B,C) = A A A 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 F(A,B,C) = m(0,4,5,7) C C = AC + B’C’ A AB B B 11 10 00 01 C 0 1 C B KarnaughMaps • Numbering scheme based on Gray–code • e.g., 00, 01, 11, 10 • Only a single bit changes in code for adjacent map cells Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  38. Karnaugh Maps for Four Inputs Represent functions of 4 inputs with 16 minterms Use same rules developed for 3-input functions Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  39. A 0 1 0 0 1 0 0 1 D 1 1 1 1 1 1 1 1 C B Karnaugh map: 4-variable example + A’BD C + B’D’ AB CD F(A,B,C,D) = m(0,2,5,8,9,10,11,12,13,14,15)F = Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  40. C f A’D 0 0 0 1 1 0 1 1 0 0 11 00 10 01 0 1 B A D 1 X 11 00 0 0 0 1 0 0 1 1 0 0 1 1 1 0 1 0 0 X X 0 0 0 0 1 01 10 0 0 0 D 0 0 1 1 0 0 C 1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 B + + Karnaugh maps: Don’t cares + C’D A AB CD X 0 X 1 0 0 1 1 0 0 0 0 1 1 0 X • f(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13) • without don't cares • f = Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  41. Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

  42. Thank You Saras M. Srivastava PGT CS, KV IISc, Bangalore 12

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