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Understanding S12X Memory Scheme

CHANGE THE FUTURE. May 2007. Understanding S12X Memory Scheme. Christian Michel-Sendis RTAC – TIC Mexico. Agenda. Introduction S12X Programming model S12X Memory resources Understanding Memory Paging: Local memory map and Paged Memory Lab 1: Accessing paged data

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Understanding S12X Memory Scheme

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  1. CHANGE THE FUTURE May 2007 Understanding S12X Memory Scheme • Christian Michel-Sendis RTAC – TIC Mexico

  2. Agenda • Introduction • S12X Programming model • S12X Memory resources • Understanding Memory Paging: • Local memory map and Paged Memory • Lab 1: Accessing paged data • Lab2: Linking Big Objects • Global Memory map • Lab 3: Working with Global Addresses • -Map Option in the XEP100 • Lab4: -Map Option on XEP100 • Working with the XGATE Module: • XINT Module • XGATE Module • Discussion :Understanding a template XGATE project

  3. AccA AccB 7 0 7 0 AccD 15 0 IX 15 0 IY 15 0 SP 15 0 PC 15 0 CCR 15 0 Introduction : S12X CPU – Programmer’s Model 2 - 8bit Accumulators (A & B) or 16bit Accumulator (D) Index Registers (X & Y) Stack Pointer Program Counter Condition Code Register (now 16 bits)

  4. AccA AccB 7 0 7 0 AccD 15 0 IX 15 0 IY 15 0 SP 15 0 PC 15 0 CCR 15 0 Introduction : S12X CPU – Programmer’s Model S12X CPU’s instructions are designed to work with 16-bit addresses. The PC register for example, will only be able to point at instructions located in a 16 bit address range, from 0x0000 to 0xFFFF. This range of addresses is what can DIRECTLY be “seen” by the S12XCPU. This 16-bit addressable working space is what we call the S12X CPU’sLocal Map A 16-bit addressable space corresponds to 64 Kilobytes of memory

  5. Introduction : S12X CPU Local Map 0x0000 0xFFFF So, the Local Map is a 64K working space where the CPU, through the use of its instruction set, can directly read and store data and code into the on-chip memory resources On-Chip Memory resources : FLASH RAM EEPROM I/O Registers 64 Kilobytes

  6. Introduction : S12X CPU Local Map 0x0000 0x0800 0x1000 0x4000 0xFFFF • How are these On-Chip Memory resources placed in the map ? • FLASH • RAM • EEPROM • I/O Registers • The Local Map is split into 4 different regions • Depending on the address pointed to in the local map, we will be accessing the different resources. • These are the corresponding boundary addresses 2K REGISTERS 2K EEPROM 12K RAM 48K FLASH

  7. We have > 1 MB of memory resources that we need to access! Introduction : S12X Memory Resources • What is the problem? Let’s take a look at the memory resources available in an S12X • (Figure shows an S12XEP100 device) 2K Registers

  8. Understanding Memory Paging. 0x0000 0x0800 0x1000 0x4000 0xFFFF 2K REGISTERS • We have more memory than we can address with • 16 bits! • The Registers do not cause conflict because they are not bigger than 2K. • EEPROM, RAM and FLASH do cause conflict because we have more available memory than space reserved for these resources in the Local Memory Map • How can we access all of the available memory from the local memory map? • Memory Paging for EEPROM, RAM and FLASH is used as workaround for this Local Map limitation! 2K EEPROM 12K RAM 48K FLASH

  9. Understanding Memory Paging. The basic idea behind memory paging is to divide the total amount of memory into groups of bytes of fixed sizes. Each group of bytes is called a PAGE, or, a BANK * This division into pages is NOT a real physical division. It will just be seen as a division by the user’s program. A hardware mechanism will allow us to DISPLAY inside the local Map The contents of a given page. Let’s see this explained in a more graphical way : *Do not confuse Pages or Banks with memory Blocks.

  10. 2K REGISTERS 2K EEPROM 12K RAM 48K FLASH 0x0000 0x0800 0x1000 0x4000 0xFFFF Understanding Memory Paging. We are going to graphically explain the idea of memory paging for the FLASH The same mechanism is used for RAM and EEPROM.

  11. 16K FLASH 16K FLASH 16K FLASH 1 MB FLASH 0x0000 0x0800 0x1000 0x4000 0x8000 0xC000 0xFFFF 2K REGISTERS FLASH Paging 2K EEPROM PAGE 0xE0 1 - The flash is “cut” in pages of 16K 2- In the Local Map, the 48K FLASH region is subdivided in 3 - 16K regions. 3- Any 16K page from the 1MB physical array can be virtually displayed on the Local’s map middle 16K page, by writing the page number to a special register. 12K RAM 16K Page 48K FLASH PAGE 0xFE Register PPAGE= 0xFE Register PPAGE=0xE0

  12. 16K FLASH FLASH PAGE WINDOW 16K FLASH 4K EEPROM 0x0000 0x0800 0x0C00 0x1000 0x4000 0x8000 0xC000 0xFFFF 2K REGISTERS EEPROM Paging PAGE 0xFC 1K EEPROM 2K EEPROM 1K Page 1K EEPROM 1- The EEPROM is “cut” in 1K pages. 2- In the Local Map, the 2K EEPROM region is subdivided in 2- 1K regions. 3- Any 1K page from the 4K physical array can be virtually displayed on the Local’s map upper 1K page, by writing the page number to a special register. 12K RAM Register EPAGE= 0xFC

  13. 16K FLASH FLASH PAGE WINDOW 16K FLASH 0x0000 0x0800 0x0C00 0x1000 0x2000 0x4000 0x8000 0xC000 0xFFFF 2K REGISTERS RAM Paging EEPROM WINDOW 1K EEPROM 1 - The RAM is “cut” in pages of 4K 2- In the Local Map, the 12K FLASH region is subdivided in 2 regions 4K and 8K big. 3- Any 4K page from the 64K physical array can be virtually displayed on the Local’s map upper 4K page, by writing the RAM page number to a special register 4K RAM 12K RAM 4K Page 8K RAM PAGE 0xFD Register RPAGE= 0xFD 64K RAM

  14. 0x0000 0x0800 0x0C00 0x1000 0x2000 0x4000 0x8000 0xC000 0xFFFF 2K REGISTERS 1K EEPROM WINDOW 1K EEPROM 4K RAM WINDOW 8K RAM 16K FLASH FLASH PAGE WINDOW 16K FLASH Other Memory Regions Q: What about the other memory regions in the local map ? A : They are mapped to FIXED locations on the physical memory arrays. The physical addresses that are mapped here are defined at chip integration. Because you do not need to handle a PAGE register to access this memory, these regions are called UNPAGED or UNBANKED

  15. RPAGE EPAGE PPAGE Memory Mapping Control Module (MMC) Paging Mechanism • Paging Mechanism: We have seen how to make it work. Now let’s see what’s behind this : It’s not magic. Local Memory Map ALL Available Physical Memory

  16. Paging Mechanism • MMC Module : It allows to converta 16 bits address supplied by the CPU to a 23-bit address used to access the specific global (physical) memory. • The additional information is supplied by the PAGE registers • (RPAGE, EPAGE, PPAGE) which are 8-bits long each. Global Memory 16 bits Address CPUS12X MMC 23 bits Address EPAGE RPAGE PPAGE

  17. 0x00-0000 0x7F-FFFF The Global Map • A 23 bit address allows to reference an address space of 2^23 = 8 MBytes! • Address range is now 0x000000 – 0x7FFFFF. • More addressable memory than we have available! • How are our memory resources placed in this Global Map?

  18. ~1MB RAM AREA 256 Kb EEPROM AREA 2.75 MB EXTERNAL SPACE AREA 4MB FLASH AREA 0x00_0000 0x00_0800 0x10_0000 0x14_0000 0x40_0000 0x7F-FFFF 2K REGISTERS The Global Memory Map • How are our memory resources placed in this Global Map? • Dedicated address areas are devoted to each memory resource. • Depending on how much memory each device has, the map will be filled from the bottom-up. • The areas that are left empty are said to be “unimplemented”

  19. 0x00_0000 0x00_0800 0x10_0000 0x14_0000 0x40_0000 0x7F-FFFF 2K REGISTERS ~1MB RAM AREA 256 Kb EEPROM AREA EXTERNAL SPACE AREA 4MB FLASH AREA 16K 16K 16K 16K 16K • How is paging reflected in the Global Memory Map? • The designation of page numbers inside each available memory resource is done also from the bottom – up, starting with page number 0xFF. • (Page 0xFF corresponds to the memory page with the highest addresses, for each resource) • Example for the FLASH resource : 4MB FLASH AREA PAGE 0xC0 PAGE 0xFB PAGE 0xFC PAGE 0xFD PAGE 0xFE PAGE 0xFF

  20. Local RAM Window Address 12 lower bits RPAGE Register 8 bits RPAGE 8 bits How do we translate a local address to a global address? For a local address inside the RAM window page, the following conversion is done by the MMC: Local addresses concerned by RAM WINDOW : 0x1000 – 0x1FFF All these addresses share the same upper nibble value (1) Real information is contained in the lower 3 nibbles. Values 0x000-FFF (12 bits) These 12 bits represent the OFFSET of the value inside the RAM PAGE The RPAGE Register is included with all its 8 bits It points to the relevant RAM PAGE among the 256 theoretically possible. The 3-bit FIXED value of 0-0-0 is prepended to the global address This simply fixes the position of the RAM area inside the global map. 3-bit fixed value 0 0 0 Bit 22 Bit 19 Bit 11 Bit 0 GLOBAL ADDRESS [ 22 : 0]

  21. 0x0000 0x0800 0x0BFF 0x0C00 0x1000 0x1FFF 0x2000 0x4000 0x8000 0xBFFF 0xC000 0xFFFF 2K REGISTERS 1K EEPROM WINDOW 1K EEPROM 4K RAM WINDOW 8K RAM 16K FLASH FLASH PAGE WINDOW 16K FLASH Local map (for reference) EEPROM WINDOW Addresses : 0x0800-0x0BFF RAM WINDOW Addresses: 0x1000-0x1FFF FLASH WINDOW Addresses: 0x8000-0xBFFF

  22. Conversion into global addresses for the FLASH and EEPROM WINDOWS • An analogous conversion exists: These figures are directly taken from the Device’s datasheet, MMC chapter.

  23. FLASH PAGE 0xFD FLASH PAGE 0xFF 0x0000 0x0800 0x0C00 0x1000 0x2000 0x4000 0x8000 0xC000 0xFFFF Unbanked Pages in the Local Map 2K REGISTERS 1K EEPROM WINDOW 1K EEPROM EEPROM PAGE 0xFF 4K RAM WINDOW Let’s go back to our Local Map. Remember we have Unbanked areas? Where do these areas point to ? Specific addresses of the global memory map corresponding to these page numbers are ALWAYS visible there. RAM PAGE 0xFE RAM PAGE 0xFF 8K RAM 16K FLASH FLASH PAGE WINDOW 16K FLASH

  24. Paging mechanism Conclusions • From this we can conclude : • 1) There are memory areas that can ALWAYS be accessed in the local map without the need of playing with page registers. (unbanked areas) • 2) There are memory areas that cannot be reached directly in the local map and • HAVE TO be accessed by writing to page registers (banked areas) • Q : Do I have to write to the Page registers every time I want to access a function or variable placed in banked memory? • A: You can if you want to, or you can let the C-compiler do it for you ! • OK, so, how do I make this work by using CodeWarrior ?

  25. LAB1 : Using Paged RAM • Please Open the project called LAB1_Using_Paged_RAM • Make sure you have selected the “Softec HCS12” target • Connect your DEMO9S12XEP100 board to the USB port of your PC

  26. Conclusions from LAB 1 • Inside your code use the appropriate #pragma statement • #pragma DATA_SEG __RPAGE_SEG segment name where segment name is a placement location that goes into paged RAM • Pointers pointing to ram paged data need to be qualified with “__rptr” and will be 3 bytes big. • Add the –D__FAR_DATA option to the compiler if using initialized ram variables. • We introduced the notion of “logical addresses”

  27. LAB2 : Allocating Big Objects • Please Open the project called LAB2_Allocating_Big_Objects • Make sure you have selected the “Softec HCS12” target • Connect your DEMO9S12XEP100 board to the USB port of your PC

  28. Conclusions from LAB 2 • Paging allows to access ALL of the memory resources, • But introduces a limitation : • Sizes of objects to be allocated in paged memory cannot exceed the page size. • RAM paged objects limited to <4 K • EEPROM paged objects limited to <1K • FLASHED Paged object limited to <16K • An alternative for RAM objects >4K is to use the 8K unpaged ram area in the local map. • (Flash objects cannot benefit from the two 16K unpaged flash areas because these areas are not contiguous)

  29. Global Addressing • Lab 2 helped us to become aware of a limitation on the paging approach, especially prohibitive when attempting to allocate big objects. • Many applications need to allow storing of single objects, especially single constant objects like: • Large Look-up tables • Bitmap images • Sound • How to overcome this limitation?

  30. Global Addressing • ... Global Addressing is the answer! • Global addressing allows us to access continuous ranges of 64Kbytesdirectly from the Global Memory map. • A big 64K page window controlled by a new register, the GPAGE register, will be able to show us in a “Global View Window” a contiguous 64K space that is directly a view of the Global Memory Map. • Global addressing was mainly introduced to allow the linking of objects of up to 64K.

  31. ~1MB RAM AREA 256 Kb EEPROM AREA EXTERNAL SPACE AREA 4MB FLASH AREA 64K GPAGE Register Global Addressing 2K REGISTERS A new register is introduced : GPAGE. The GPAGE register controls what is displayed in the Global View window. In order to “SWITCH” to global view, the CPU HAS TO use SPECIAL Global Instructions. Like so, the Local Map is not perturbed. 0x0000 0xFFFF CPU-Accessible 64K Global View Window

  32. Global Addressing • The upper byte of the 23-bit global address must be written to GPAGE in order to display the corresponding 64K region of the global memory map. • Example : Writing 7E to GPAGE will result in the Global View Window displaying the contents of addresses 7E_0000 to 7E_FFFF. • Remember that ONLY special instructions can access the Global View Window. These are called Global instructions and have the form • GLDxx and GSTxx

  33. GPAGE[6:0] AB[15:0] GAB[22:0] Global Address • HCS12X has a complete set of Load & Store instructions to allow the 7 bit global address register to form a 23 bit global address: GLDAA,GLDAB,GLDD,GLDX,GLDY,GLDS,GSTAA,GSTAB,GSTD,GSTX,GSTY,GSTS • If such an instruction is executed the address is concatenated from the new 7-Bit GPAGE register + standard 16Bit address • 23Bit address = {7-Bit GPAGE, 16 Bit address}

  34. Converting from Logical Addresses to Global Addresses. 4MB FLASH AREA Logical Addresses (Banked addresses) Global Addresses ... 0xFC_BFFF 0xFD_8000 PAGE 0xFC 0x7F_3FFF 0x7F_4000 PAGE 0xFD 0x7F_7FFF 0x7F_8000 0xFD_BFFF 0xFE_8000 PAGE 0xFE PAGE 0xFF 0x7F_BFFF 0x7F_C000 0xFE_BFFF 0xFF_8000 0xFF_BFFF 0x7F_FFFF

  35. LAB 3 : Using Global Addressing to Link Big Objects • Please Open the project called LAB3_Using_Global_Addressing • Make sure you have selected the “Softec HCS12” target • Connect your DEMO9S12XEP100 board to the USB port of your PC

  36. Conclusions from LAB 3 • To use global addressing : • 1)Edit your prm file and declare a memory area using global addresses • 2)Append the character ‘G to these addresses to let the linker know they are global. • 3)Remove any double declaration pertaining to this area and create a placement section for this area • 4)Inside your code use the appropriate #pragma statement • #pragma CONST_SEG __GPAGE_SEG segment name • 5) Pointers pointing to global data need to be qualified with “__far” and will be 3 • bytes in length. • 6)Add the –D__FAR_DATA option to the compiler if using initialized ram variables.

  37. Converting from Logical Addresses to Global Addresses. • Hint : Inside the debugger you can open a small application that converts addresses. To do so: • Click on Component  Open  HCS12XAdrMap • Or you can directly open this application by going to : • C:\Program Files\Freescale\Codewarrior for HC12 V4.6\Prog • and clicking on HCS12XAdrMap.exe

  38. Conclusions from LAB 3 (Continued) • If global addressing has less limitations than using a banked addressing, why don’t we just always use global addressing? • Global instructions have slower execution time • and generate bigger code size. • Global addressing is mostly intended to be used with constants or data and not with functions. Besides, will you really have a function bigger than 16K? • Both Global Addressing and Banked Addressing can co-exist in the same project!

  39. -Map Option in the XEP100 • –Map Option This option sets the memory mapping for addresses between 0x4000 and 0x7FFF for HCS12XE. This mapping is determined by the  MMC control register (the ROMHM and RAMHM bits) and the compiler must be aware of the current setting to correctly perform address translations. Syntax -Map(RAM|FLASH|Exernal) ; Example    -MapRAM RAM: accesses to 0x4000–0x7FFF will be mapped to 0x0F_C000-0x0F_FFFF in the global memory space (RAM area). FLASH: accesses to 0x4000–0x7FFF will be mapped to 0x7F_4000-0x7F_7FFF in the global memory space (FLASH). External: accesses to 0x4000–0x7FFF will be mapped to 0x14_4000-0x14_7FFF in the global memory space (external access).

  40. -Map Option in XEP100

  41. Working with XGATE: Basics.

  42. What is XGATE? • XGATE is a programmable core • 16bit RISC engine • Instruction set optimised for data manipulation • Runs at up to 2x CPU bus speed • Driven by interrupt controller • Program code stored in RAM (or Flash) • Accesses RAM, peripherals and Flash

  43. XGATE Concept • The idea of the XGATE was born out of the need to greatly improve application responsiveness and coherency through a reduction in the interrupt loading on the main CPU. • Allow sequences of interrupt instructions to be executed in parallel with the normal CPU application execution. • “Share the work with others”

  44. S12 ! CPU Stalls Application code to service IRQ CPU Running application code CPU Running application code S12X CPU Running application code CPU Running application code CPU Running application code XGATE stopped XGATE stopped XGATE completely handles the IRQ Interrupt request Interrupt complete Interrupt Processing Application Example

  45. XGATE Objective • Interrupts from the interrupt controller hardware can be routed to the XGATE or to the CPU. • Any Interrupt routed to the XGATE will remove load from the CPU. • A switch directs the interrupt signals to the CPU or to the XGATE. • The XGATE can also Interrupts the CPU when the task is finished.

  46. R0=0 15 0 R1 = Variable Base 15 0 R2 15 0 R3 15 0 R4 15 0 R5 15 0 R6 15 0 R7 15 0 PC 15 0 CCR (N,V,C,Z) 15 0 XGATE Programmer’s Model 16-bit RISC Engine • 16bit RISC architecture • Rich register set • R0 forced to have value 0 • R1 initialised automatically by interrupt controller but can be reused • R2 – R7 general purpose • Full 16bit program counter • Simple Condition Code Register • No stack pointer • Subroutine support exists in instruction set Event driven

  47. R0=0 15 0 R1 = Variable Base 15 0 R2 15 0 R3 15 0 R4 15 0 R5 15 0 R6 15 0 R7 15 0 PC 15 0 CCR (N,V,C,Z) 15 0 XGATE Instruction set overview • Operates at 50MHz = 10ns cycle time • (for XEP100) • 1 cycle for all register-based instructions • 2 cycles for load and store instructions • 2 cycles for branches, if taken, else 1 cycle • Fixed 16-bit opcode length optimised for • Data movement and logic • Simple fast implementation

  48. R0=0 0 15 R1 = Base 0 15 R2 0 15 R3 0 15 R4 0 15 R5 0 15 R6 R6 0 0 15 15 PC 0 15 CCR (N,V,C,Z) 0 15 XGATE Instruction Set • The instruction set is optimised for fast data handling and response to events • 1..15 bit shift or rotate in one cycle • Word addition/subtraction in one cycle • 16-bit parity calculation in one cycle • Store word to memory in two cycles • Set/Clear semaphore in two cycles • Bit stuffing and extraction in one cycle • One cycle = 10 ns ( for the XEP100) • No multiply or divide instructions

  49. XGATE Instruction Set • Traditional RISC Model : “C”-Compiler friendly • Strict Load/Store Architecture • All instructions involve at least one register • Register addressing modes • Immediate 8-Bit, 4-Bit • Triadic Rd = Rs1 op Rs2 • Dyadic Rd = Rd op Rs • Monadic Function(Rd) • Inherent no register needed

  50. Complements strengths of CPU • XGATE has strengths that complement the CPU • Interrupt response time • XGATE has no need to save or recover context • Bit shifting and manipulation • N-bit shifts and N-bit insertion/extraction in one cycle • Bitwise parity in one cycle • Runs as fast as program store will allow • Execution out of RAM as fast as 100MHz

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