1 / 4

J. Nieto on behalf of

Real time plasma disruptions detection in JET implemented with the ITMS platform using FPGA based IDAQ. J. Nieto on behalf of M. Ruiz 1 , J. Vega 2 , G. Ratta 2 , E. Barrera 1 , A. Murari 3 , R. Meléndez 1 , and JET EFDA contributors 1 Universidad Politécnica de Madrid

brett-vincent
Download Presentation

J. Nieto on behalf of

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Real time plasma disruptions detection in JET implemented with the ITMS platform using FPGA based IDAQ J. Nieto on behalf of M. Ruiz1, J. Vega2, G. Ratta2, E. Barrera1, A. Murari3, R. Meléndez1, and JET EFDA contributors 1 Universidad Politécnica de Madrid 2 Asociación EURATOM/CIEMAT paraFusión 3 Consorzio RFX – Associazione EURATOM ENEA per la Fusione

  2. Objectives and methodology • To implement in real time a pattern recognition algorithm for disruption detection using commercial platforms based in PXI and PXIe. • To use FPGA based DAQ cards (intelligent data acquisition) for implementing the real time disruption detection (RTDD) system.

  3. Implementation IDAQ Signal generation

  4. Implementation & Conclusions • IDAQ implements FFT analysis and spectral deviation. • Total Slices: 61.6% (11820 out of 19200) • Flip Flops: 45.2% (8669 out of 19200) • Total LUTs: 55.2% (10595 out of 19200) • DSP48Es: 68.8% (22 out of 32) • Block RAMs: 34.4% (11 out of 32) • SCPU executes the hyper-plane distance computation (CPU load less than 3%). Algorithm implemented in the FPGA

More Related