CROWNE C urrent R atio O utlier W ith N eighbor E stimator

1. CROWNECurrent Ratio Outlier With Neighbor Estimator Sagar S. Sabade Duncan M. Walker Department of Computer Science Texas A&M University College Station, TX 77843-3112 http://ee.tamu.edu/~sagar

2. Outline • Introduction • Variability in Current Ratios • Use of Wafer Spatial Information • NCR metric • Combining Multiple Parameters • Experimental Results • Conclusions

3. Introduction • IDDQ test needs to survive in DSM era • Many methods reported in literature • Goal: Reduce variance in “fault-free” IDDQ • Current Ratio (CR) • Ratio of maximum to minimum IDDQ of a chip • Within-chip IDDQ variation similar for fault-free chip (magnitudes may differ) • Ease of implementation in production

4. CR Variation for Real Chips • Can CR detect all defective chips? Smaller CR does not necessarily imply a fault-free chip – it may be a passive defect!

5. Why Use Spatial Information? Neighboring fault-free Chips have similar IDDQ For same vector

6. IDDQ (chip1) (i) Chip 1 IDDQ readings NCR (i) = Chip 2 IDDQ readings IDDQ (chip2) (i) IDDQ Vector Number Neighbor Current Ratio (NCR) • Take ratio of IDDQ of neighboring chips for samevector [details in our DFTS 02 paper] N Nbrs, k vectors N.k NCR values NCR = Max (NCR(i))

7. Single metric alone not enough to catch defects CR looks “within-chip” variability NCR considers local neighborhood variation Easy to detect passive defects with fewer vectors “CROWNE” chips Gross outlier tail Combining CR and NCR

8. Passive defects CR/NCR Combination Insights Region A Nominal CR Subtle active defects Spatial Outliers Region B CR, NCR Outliers Active defects NCR NCR Threshold Region D Nominal CR,NCR Fault-free Chips/ Good chips in Bad neighborhood Region C Outliers in Bad neighborhood 1 CR CR Threshold

9. CROWNE Chips • Chips that are okay with CR alone • But are outliers when neighboring chips are used • Are these chips • Defective?  should be rejected • Different?  okay to ship • Weak?  reliability concern

10. XY projection CR, NCR and Flush Delay

11. How does combination help us? CR NCR Delay Result Small Fast wafer region Large Resistive short/defect? Low Low Small A chip with passive defect Large in a good neighborhood Low High Small A chip with active defect Large in a bad neighborhood High Low High High Small A chip with active defect Large in a good neighborhood

12. Analysis of SEMATECH Data • 0.6  technology • 12521 chips • four test types – IDDQ, stuck-at, functional, delay • 195 IDDQ readings/chip, threshold 5 A • Screened all chips above 100 A, obvious outliers • Flush delay > 500 ns considered outlier • CR, NCR threshold decided from CDF • CR threshold 5 • NCR threshold 10

13. CR/NCR scatter plot for low CR More passive More active

14. CR/NCR scatter plots • Some delay failures can be identified by NCR • No systematic pattern

15. Flush delay/NCR scatter plot • Poor correlation between NCR and flush delay • NCR cannot screen delay failures well

16. Conclusion • Low CR is deceptive • Can be passive defect; reliability hazard • Spatial information useful (e.g. NCR) • Combination of CR/NCR has better outlier screening • NCR not suited for delay failures • Additional screen needed • More data analysis needed to validate claims