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Protocol Transducer Synthesis

Protocol Transducer Synthesis. Masahiro Fujita VLSI Design and Education Center (VDEC) The University of Tokyo. Background and Objective. Design period of VLSI is becoming long… IP-Based design methodology is an attractive solution.

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Protocol Transducer Synthesis

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  1. Protocol Transducer Synthesis Masahiro Fujita VLSI Design and Education Center (VDEC) The University of Tokyo

  2. Background and Objective • Design period of VLSI is becoming long… • IP-Based design methodology is an attractive solution. • In IP-Based design, compatibility of protocols among the IPs can be a big problem. • Design of a protocol transducer is time consuming. Automatic Transducer Synthesis is necessary.

  3. Specifications in Regular Expression Transducer FSM Exploration Algorithm Regular Expression Parser Protocol A Protocol B Specifications in Automata Previous Work • Passerone’s work • Synthesize a protocol transducer from two specifications of input protocols

  4. Passerone’s Method -problems- • Hard to deal with complex automata, because the search space becomes very large. • Cannot deal with “Loops” in the input automata, because the search space becomes infinite.

  5. Research Objective • Automatically synthesize protocol transducers even for complex protocol, by extending Passerone’s Method. • Basic Idea: • Partition the exploration space into some small ones. • Construct the whole transducer from the portions.

  6. Outline of Proposed Method • Protocol Modeling Method • Sequence Level Synthesis • Automaton Level Synthesis • Construction of whole Transducer Protocol A Sequence A1 Automaton FSM Transducer Automaton FSM Sequence A2 Automaton FSM Automaton FSM Protocol B Sequence B1 Automaton Automaton Sequence B2 Automaton Automaton

  7. 1.Protocol Modeling Method • If a protocol is modeled as an automaton, the automaton tends to be very large and complex. • We propose partitioning a protocol into some “sequences”. And make each sequence related to some automata. Protocol Sequence = Sequence = Automata • A sequence corresponds to one transaction; for example Read, Write, etc. • A sequence has one or two automata. • Every automaton in a sequence must have paths which return to initial state. • We call the initial state “idle state”.

  8. 1.Protocol Modeling Method • The number of automata related to a sequence is determined by protocol type: • Protocol Types: • Blocking Protocol A protocol whose master cannot issue another request until the slave returns the response. • Non-Blocking Protocol A protocol whose master can issue another request before arrival of the response. Slave have to respond in order of the requests. • Out-of-Order Protocol A protocol whose master can issue another request before arrival of the response. Slave can respond regardless of the requested-order. Each sequence in a Blocking Protocol is related to 1 automaton, called “Blocking Automaton” Each sequence in a Non-Blocking Protocol is related to 2 automata; “Request Automaton” and “Response Automaton”. Each sequence in a Out-of-Order Protocol is also related to 2 automata; “Request Automaton” and “Response Automaton”.

  9. 2.Sequence level Transducer Synthesis • We synthesized partial transducers from each sequence pair. • Making pair is not automated yet… Construction (explained later) Protocol A Protocol B Read Sequence Read Sequence Protocol A Protocol B Transducer Transducer (Read Seq.) Write Sequence Write Sequence Transducer (Write Seq.) ... ... ...

  10. 3.Automaton level Transducer Synthesis • Automaton Level Synthesis is done by extended Passerone’s Method. • Input: two automata • Output: a FSM • The extensions are following: • Handling of Loops • Multiple Data sequences

  11. Handling of Loops in automata • Every automaton in the sequences has paths which returns to idle state. • So, all automata have loops in themselves. • This prevents from being applied Passerone’s method. i i i i Exploration (Passerone’s Method) e i i e e

  12. SS = Kernel Graph Shell Graph Multiple Data Sequences However, the insersion of “end state” cannot deal with “internal loop” shown in the figure. We call a sequence which includes this kind of automata “Multiple Data Sequence”. We dealt with Multiple Data Sequence by introducing super state

  13. SS C SS B Super State C Multiple Data Sequences SS A Exploration Super State A Exploration Super State B

  14. The developed tool • We implemented our synthesis method on a fully original tool. • It accepts protocol specifications in the form of XML files as its inputs. • Its output is the RTL description of the protocol transducer written in Verilog.

  15. Screen Shot of the tool Loaded Protocol Specifications List of the synthesized partial transducers Details of the master’s protocol and its hierarchical structure Details of the slave’s protocol and its hierarchical structure

  16. Input of the tool (Protocol Spec. in XML File) <protocol name=“A”> <ports> <port name=“Cmd” width=“3” driver=“master”> </ports> <sequence> <automaton type=“REQUEST”> <node id=“1” name=“State1”> … <edge from=“1” to=“2”> <transaction port=“Cmd” value=“3’b010”> </edge> … </automaton> <automaton type=“RESPONSE”> … </automaton> </sequence> … </protocol>

  17. Protocol Spec. Sequence Request Automaton Response Automaton Input of the tool (Protocol Spec. in XML File) <protocol name=“A”> <ports> <port name=“Cmd” width=“3” driver=“master”> </ports> <sequence> <automaton type=“REQUEST”> <node id=“1” name=“State1”> … <edge from=“1” to=“2”> <transaction port=“Cmd” value=“3’b010”> </edge> … </automaton> <automaton type=“RESPONSE”> … </automaton> </sequence> … </protocol> Signal Declarations

  18. Request Response Request Response Single Read Single Read Single Write Experiment: Non-Blocking Non-Blocking MASTER: OCP (Single Read, Non-Posted Write) SLAVE: OCP (Single Read, Single Write) Non-Posted Write

  19. M_MCmd S_MCmd S_MData M_MAddr M_MData S_MAddr M_SCmdAccept S_SCmdAccept M_SResp S_SResp M_SData S_SData Test Bench Master FSM for Request (FIFO-ready) Slave Non-Posted Write Request Single Read Request Single Write Request Single Read Request WData PUSH FIFO (2bit x 4) RData PUSH Single Read Response Non-Posted Write Response Single Read Response FSM for Response (FIFO-ready) D RST CLK

  20. Single Read Request Single Read Request FIFO Push Simulation Waveform

  21. Non-Posted Write Request Single Write Request FIFO Push Simulation Waveform

  22. Single Read Response FIFO Pop Simulation Waveform

  23. Non-Posted Write Response FIFO Pop Simulation Waveform

  24. Conclusion • We showed our transducer synthesis is applicable to complex protocols by extending Passerone’s method. • The basic idea of our proposed method is to partition protocol model into portions • We implemented our method on a original tool.

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