Sep 1 st , 2008 Majd F. Sakr msakr@qatar.cmu qatar.cmu/~msakr/15447-f08/

1. CS-447– Computer Architecture M,W 2:30-3:50pmLecture 5Instruction Set Architecture Sep 1st, 2008 Majd F. Sakr msakr@qatar.cmu.edu www.qatar.cmu.edu/~msakr/15447-f08/

2. Done by now • Read the first 3 chapters of the book • Review the slides • Come see us during office hours • Working on the project

3. Program Concept • Hardwired systems are inflexible • General purpose hardware can do different tasks, given correct control signals • Instead of re-wiring, supply a new set of control signals

4. What is a program? • A sequence of steps • For each step, an arithmetic or logical operation is done • For each operation, a different set of control signals are needed

5. Execution of a Program

6. Program -> Sequence of Instructions

7. Function of Control Unit • For each operation a unique code is provided • e.g. ADD, MOVE • A hardware segment accepts the code and issues the control signals • We have a computer!

8. Computer Components: Top Level View

9. Instruction Cycle • Two steps: • Fetch • Execute

10. Fetch Cycle • Program Counter (PC) holds address of next instruction to fetch • Processor fetches instruction from memory location pointed to by PC • Increment PC (PC = PC + 1) • Unless told otherwise • Instruction loaded into Instruction Register (IR) • Processor interprets instruction

11. Execute Cycle • Processor-memory • data transfer between CPU and main memory • Processor I/O • Data transfer between CPU and I/O module • Data processing • Some arithmetic or logical operation on data • Control • Alteration of sequence of operations • e.g. jump • Combination of above

12. Application (MediaPlayer) Operating Compiler System (Windows XP) Software Assembler Instruction Set Architecture Hardware Processor Memory I/O system Datapath & Control Layout & Technology Digital Design Circuit Design Transistors Instruction Set Architecture The Language of the Computer

13. Chapter objectives • The goal of this lecture is to discuss an instruction set (a simple one), showing both how instructions are represented in hardware & the relationship between high-level programming languages (for example C-language which you know) and this more primitive one. • Next time: the different addressing modes.

14. Chapter objectives (2) • By learning how to represent instructions, you will also discover the secret of computing: the stored-program concept.

15. Translating & Starting a Program C Program Compiler Assembly Language Program Assembler Object: Machine language module Linker Executable: Machine language program

16. Translating & Optimizing a Program: TheCompiler The Compiler transforms the C program into an assembly language program, a symbolic form of what the machine understands.

17. Translating a Program: TheAssembler The Assembler transforms the Assembly program into a machine language module.

18. Stitching a Program: TheLinker The linker or link editor takes all the independently assembled machine language programs and “stitches” them together. There are three steps for the linker: 1) Place code and data modules symbolically in memory2) Determine the addresses of data and instruction labels3) Patch both the internal and external references

19. What Happens in Hardware? Instructions CPU Memory Data

20. Address Bus & Data Bus Address Bus CPU Memory Data Bus

21. Address Bus CPU Memory Data Bus Address Bus & Data Bus • Address Bus: • Names • Locations • Where to go • Data Bus: • Content • Values • Variables

22. Memory Addressing

23. Memory Memory Decoder1 to 2 Decoder1 to 2 0 0 1 1 DataBus = 1 DataBus = 2 Example of Memory with AddrBus = 1 Address Bus = 1 Address Bus = 1

24. Example of Memory with AddrBus = 1 Memory Decoder1 to 2 0 1 Data Bus = 8 Address Bus = 1

25. Memory Decoder2 to 4 0 0 1 1 0 1 0 1 DataBus = 1 Example of Memory with AddrBus = 2 Address Bus = 2

26. Memory Decoder2 to 4 0 0 1 1 0 1 0 1 DataBus = 2 Example of Memory with AddrBus = 2 Address Bus = 2

27. Example of Memory with AddrBus = 2 Memory Decoder2 to 4 1 0 0 1 1 0 1 0 Address Bus = 2 DataBus = 8

28. How does the Memory look like?

29. Memory Addresses Vs Memory Content As shown in the memory table: # locations = 64 (ML0 to ML63) => memory require 6-bits to address if the memory word-size = 11-bits => largest content in memory is 2048

30. In General we Need 2#bits = # Memory Locations If we wish to have 120 locations (120 names), then7-bitsshould be dedicated to address them(27= 128) If we first decide to dedicate 6-bits to address the memory locations, then we will be limited to 64 in their number (26= 64)

31. Instruction Set Design CPU Memory Address Bus Instructions Register File Control Data IR Functional Units Data Bus PC

32. What is an instruction set? • The complete collection of instructions that are understood by a CPU • Machine Code • Binary • Usually represented by assembly codes

33. Elements of an Instruction • Operation code (Op code) • Do this operation • Source Operand reference • To this to this value • Result Operand reference • Put the answer here

34. Operation Code (page 342) • Operation code(Opcode) • Do this operation

35. Processor Operations: In total, the # of instructions desired is 8, and these require 3-bits for controlling.

36. Registers & How Big? • CPU must have some working space (temporary storage) • Number of Registers varies between processor designs • Large enough to hold full address • Large enough to hold full data word

37. How does the Registers File look like?

38. Register Address Vs Register Content As shown in the register file: # registers = 8 (R0 to R7) => registers require 3-bits to address if the register size = 11-bits => largest content in registers is 2047

39. In General we Need 2#bits = # Registers If we wish to have 30 registers, then5-bitsshould be dedicated to address them(25= 32) If we first decide to dedicate 4-bits to address the registers, then we will be limited to 16 in their number (24= 16)

40. I want this operation to make the additionof two registers & place the result in a third one Example: Add R1, R2, R3 ; R1 = R2 + R3 Instruction Design

41. Instruction Design If in our register file we had 4 registers, requiring 2-bits for addressing each; thus the 3 operands desired (R1, R2, R3) in the Add operation require (2x3 =) 6-bits to be addressed.

42. Instruction Design: Add R0, R4, R11

43. Add R1, R2, R3 ;(= 001011011) What happens inside the CPU? 0 1 Register File I.R. 001011011 2 2 001011011 001011011 ... 3 P.C. 3 2 4 FunctionalUnits 5 6 7 Memory CPU

44. Add R1, R2, R3 ;(= 001011011) R1 R3 NextInstruction 011111111 001010101 I.R. 001011011 R2 010101010 ... 3 P.C. 4 010101010 001010101 + CPU

45. Hypothetical Machine Consider the following hypothetical machine: # registers = 16 {R0 to R15} require 4-bits to address them (24 = 16) # memory locations = 256 {M0 to M255} require 8-bits to address them (28 = 256)

46. Hypothetical Machine (cont’d) # instructions = 32 {Inst0 to Inst31} require 5-bits to be controlled (25 = 32) where Inst15 = Add (instruction # 15) & Inst9 = Load (instruction # 9)

47. Example 1: Add R0, R4, R11

48. The instruction In fact, each piece of an instruction can be considered as an individual number, & placing these numbers side by side forms the instruction.

49. Example 2: Load R13, 127

50. The instruction In fact, the instruction format Example: OpCode, Operand, Operand, Operandis fixed only for a specific operation