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Data Output Block Verification

Data Output Block Verification. Tomasz Hemperek. Steps. RTL simulation (global and local test bench) Synthesis (Design Compiler) Equivalent check (Formality) P lace and Route (SOC Encouter) S tatic Timing Analysis (sign off) – Prime Time Corners: TT (25C, 1.2V – RC typ)

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Data Output Block Verification

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  1. Data Output Block Verification Tomasz Hemperek

  2. Steps • RTL simulation (global and local test bench) • Synthesis (Design Compiler) • Equivalent check (Formality) • Place and Route (SOC Encouter) • Static Timing Analysis (sign off) – Prime Time • Corners: • TT (25C, 1.2V – RC typ) • FF (-55C, 1.32V – RC min) • SS (70C, 1.08V – RC max) • Post P&R digital simulation (SDF corners) • Analog extraction & simulation

  3. Layout (with T3) ~100x150um

  4. Analog simulation (QRC) Ultrasim

  5. Mixed-Signal Simulation (ADMS-eldo) DIGITAL TB ANALOG TB TRANSCRIPT: # RECIVER: Header - LV1Id=[ 10] BC=[12] Service Word=[0] ] # RECIVER: Data - col=[12] row=[124] Tot=[ 9, 5] (pix=[ 3819, 3820]) # RECIVER: Header - LV1Id=[ 13] BC=[13] Service Word=[0] ] # RECIVER: Data - col=[13] row=[124] Tot=[ 9, 5] (pix=[ 4155, 4156]) ALL SCRIPTS AND OUTPUT FILES ARE IN REPOSITORY! (MIXED-SIGNAL SOON)

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