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Data Output Block Verification

Data Output Block Verification. Tomasz Hemperek. Steps. RTL simulation (global and local test bench) Synthesis (Design Compiler) Equivalent check (Formality) Place and Route (SOC Encouter) S tatic Timing Analysis (sign off) – Prime Time Corners: TT (25C, 1.2V – RC typ)

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Data Output Block Verification

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  1. Data Output Block Verification Tomasz Hemperek

  2. Steps • RTL simulation (global and local test bench) • Synthesis (Design Compiler) • Equivalent check (Formality) • Place and Route (SOC Encouter) • Static Timing Analysis (sign off) – Prime Time • Corners: • TT (25C, 1.2V – RC typ) • FF (-55C, 1.32V – RC min) • SS (70C, 1.08V – RC max) • Post P&R digital simulation (SDF corners) • Analog extraction & simulation

  3. Extracted simulation • extracted with coupling C • RCC extraction simulated (0.5p load on ouputs) Works with 0.5V also!

  4. Scan chain • TetraMax patterns simulated with correnres and analog RCC netlist (ADIT for 10us ) // Uncollapsed Stuck Fault Summary Report // ----------------------------------------------- // fault class code #faults // ------------------------------ ---- --------- // Detected DT 2183 // Possibly detected PT 0 // Undetectable UD 37 // ATPG untestable AU 588 // Not detected ND 4 // ----------------------------------------------- // total faults 2812 // test coverage 78.67% // ----------------------------------------------- // // Pattern Summary Report // ----------------------------------------------- // #internal patterns 27 // #basic_scan patterns 27 // -----------------------------------------------

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