Lecture 14 PicoBlaze Overview

1. Lecture 14PicoBlaze Overview ECE 448 – FPGA and ASIC Design with VHDL

2. Required reading • P. Chu, FPGA Prototyping by VHDL Examples • Chapter 14, PicoBlaze Overview Recommended reading • K. Chapman, PicoBlaze for Spartan-6, Virtex-6, and 7-Series (KCPSM6) ECE 448 – FPGA and ASIC Design with VHDL

3. Block diagram of a Single-Purpose Processor (FSMD – Finite State Machine with Datapath) ctrl ECE 448 – FPGA and ASIC Design with VHDL

4. Block diagram of a General-Purpose Processor (Microcontroller) ECE 448 – FPGA and ASIC Design with VHDL

5. PicoBlaze-3 ECE 448 – FPGA and ASIC Design with VHDL

6. PicoBlaze-3 Overview

7. PicoBlaze-6 Overview

8. PicoBlaze-6 Overview

9. Size of PicoBlaze-6 in Spartan 6 Make an educated guess Resource Utilization in CLB Slices ? Number of PicoBlaze-6 cores fitting inside of the Spartan-6 FPGA (XC6SLX16) used on the Nexys3 FPGA board ?

10. Size of PicoBlaze-6 in Spartan 6 • Resource Utilization in CLB Slices • 26 CLB Slices • 1.1% of Spartan-6 used in Nexys3 • Number of PicoBlaze-6 cores fitting inside of the Spartan-6 • FPGA (XC6SLX16) used in the Nexys3 FPGA board • 87 PicoBlaze cores

11. Speed of PicoBlaze-6 in Spartan 6 Make an educated guess Maximum Clock Frequency ? Maximum number of instructions per second ?

12. Speed of PicoBlaze-6 in Spartan 6 • Maximum Clock Frequency • 105 MHz • Maximum number of instructions per second • 52.5 millions of instructions per second (MIPS)

13. Register File of PicoBlaze-3 8-bit Address s0 s1 s2 s3 s4 s5 s6 s7 0 7 0 1 0 7 2 7 0 3 7 0 4 7 0 5 7 0 16 Registers 7 0 6 7 0 7 sF F 7 0

14. Register File of PicoBlaze-6 • Instructions • REGBANK A • REGBANK B • used to switch between banks • Only one set of flags • Z, C, I • Very useful for • interrupt service routines

15. Definition of Flags Flags are set or reset after ALU operations Zero flag - Z zero condition Z = 1 if result = 0 0 otherwise overflow, underflow, or various conditions Carry flag - C Example* C = 1 if result > 28-1 (for addition) or result < 0 (for subtraction) 0 otherwise *Applies only to addition or subtraction related instructions, refer to the following slides otherwise

16. Interface of PicoBlaze-3 KCPSM = constant (K) coded programmable state machine ECE 448 – FPGA and ASIC Design with VHDL

17. Interface of PicoBlaze-3 ECE 448 – FPGA and ASIC Design with VHDL

18. Interface of PicoBlaze-6 ECE 448 – FPGA and ASIC Design with VHDL

19. Interface of PicoBlaze-6 ECE 448 – FPGA and ASIC Design with VHDL

20. Additional Ports of PicoBlaze-6 ECE 448 – FPGA and ASIC Design with VHDL

21. Generics of PicoBlaze-6 ECE 448 – FPGA and ASIC Design with VHDL

22. PicoBlaze-6 Instantiation ECE 448 – FPGA and ASIC Design with VHDL

23. Development Flow of a System with PicoBlaze ECE 448 – FPGA and ASIC Design with VHDL

24. PicoBlaze-3 Programming Model ECE 448 – FPGA and ASIC Design with VHDL

25. PicoBlaze-6 Programming Model Bank B Bank A FFC FFD FFE FFF ECE 448 – FPGA and ASIC Design with VHDL

26. Syntax and Terminology Syntax Example Definition sX KK PORT(KK) PORT((sX)) RAM(KK) Value at register 7 Value ab (in hex) Input value from port 2 Input value from port specified by register a Value from RAM location 4 s7 ab PORT(2) PORT((sa)) RAM(4)

27. Addressing modes Immediate mode SUB s7, 07 ADDCY s2, 08 s7 – 07  s7 s2 + 08 + C  s2 Direct mode sa + sf  sa PORT(2a)  s5 ADD sa, sf INPUT s5, 2a Indirect mode s3 RAM((sa)) PORT((s2))  s9 STORE s3, (sa) INPUT s9, (s2)

28. PicoBlaze ALU Instruction Set Summary (1)

29. PicoBlaze ALU Instruction Set Summary (2)

30. PicoBlaze ALU Instruction Set Summary (3)