ECE 331 – Digital System Design

1. Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.

2. ECE 331 - Digital Systems Design Design conception DESIGN ENTRY Schematic capture VHDL Synthesis Functional simulation No Design correct? Yes Physical design Timing simulation Timing Requirements met? No Yes Chip configuration The Design Process

3. ECE 331 - Digital Systems Design Introduction to VHDL • What is VHDL? • Very High Speed Integrated Circuit (VHSIC) • Hardware • Description • Language • VHDL is a formal language for specifying the behavior and structure of a digital circuit. • Verilog is another, equally popular, hardware description language (HDL).

4. ECE 331 - Digital Systems Design Hardware Description Languages • Both VHDL and Verilog are hardware description languages. • They describe hardware! • They are not software programming languages. • This is an important, but difficult, concept to understand.

5. ECE 331 - Digital Systems Design VHDL Designs • A VHDL design is composed of two parts: • Entity • Architecture • The entity statement defines the interface to the circuit (i.e. inputs and outputs). • The architecture statement describes the implementation of the circuit.

6. ECE 331 - Digital Systems Design The Entity Statement • Defines the input and output of the design. entity entity-name isport( port-name-A: modetype; port-name-B: modetype; port-name-C: modetype; … ); end [entity][entity-name];

7. ECE 331 - Digital Systems Design Ports • Each I/O signal in the entity statement is referred to as a port. • A port is analogous to a pin on a schematic. • Similar to variables in a HLL, a port is a data object. • Can be assigned values. • Can be used in expressions.

8. ECE 331 - Digital Systems Design Mode • The mode describes the direction in which data is transferred through a port. • There are 4 different modes:

9. ECE 331 - Digital Systems Design Type • VHDL is a strongly typed language. • Data objects of different types cannot be assigned to one another without the use of a type-conversion function. • There are two broad categories of data types: • scalar • stores a single value • composite • stores multiple values

10. ECE 331 - Digital Systems Design bit scalar boolean integer character std_ulogic std_logic bit_vector composite string std_ulogic_vector std_logic_vector Types • The VHDL data types include:

11. ECE 331 - Digital Systems Design Types • The most useful types for synthesis and simulation, provided by the IEEE std_logic_1164 package, are: • std_logic • std_ulogic • std_logic_vector • std_ulogic_vector

12. ECE 331 - Digital Systems Design IEEE Standard Logic Types • Use of two-valued logic (bit and bit_vector) is generally not sufficient to simulate digital systems. • In addition to 0 and 1, Z (high-impedance), X (unknown), and U (uninitialized) are often used in digital system simulation. • The IEEE standard 1164 defines the std_logic type that has nine values: • 0, 1, Z, X, U, W, L, H, - • Use std_logic and std_logic_vector in your designs.

13. ECE 331 - Digital Systems Design The Architecture Statement • Describes the implementation of the design. • Specifies the function of the design. architecture architecture-name of entity-name is [declarations] begin architecture body end [architecture][architecture-name];

14. ECE 331 - Digital Systems Design The Architecture Statement • One or more architecture statements may be associated with an entity statement. • Only one may be referenced at a time. • Declarations • Signals and components. • Architecture body • Statements that describe the functionality of the design (i.e. the circuit).

15. ECE 331 - Digital Systems Design Architecture Body • Several different models, or styles, may be used in the architecture body, including: • Behavioral • Dataflow • Algorithmic • Structural • These models allow you to describe the design at different levels of abstraction. • Algorithms → Gates

16. ECE 331 - Digital Systems Design Behavioral Model • Specify a set of statements to model the function, or behavior, of the design. • Dataflow: uses concurrent statements • Algorithmic: uses sequential statements

17. ECE 331 - Digital Systems Design Structural Model • Specify a set of statements to instantiate and interconnect the components necessary for the design. • Components are defined separately. • Signals are used to interconnect components. • Results in a hierarchical design.

18. ECE 331 - Digital Systems Design Components • A component is a predefined element used in an hierarchical design. • Component declaration component component-name port( port-name-A: modetype; port-name-B: modetype; … ); end component;

19. ECE 331 - Digital Systems Design Components • Component instantiation label: component-name port map( port-name-A => signal-name-A, port-name-B => signal-name-B, … ); • The above mapping of port names to signal names is known as named association. • Positional association may also be used.

20. ECE 331 - Digital Systems Design Signals • A signal is used to interconnect components in an hierarchical design. • Signal declaration signal signal-name: type;

21. ECE 331 - Digital Systems Design Statements • Concurrent statements • All are executed at the same time. • The order is unimportant. • Sequential statements • Executed in the order in which they are listed. • The order is very important. • The Process statement • Sequential statements must be enclosed within a process statement.

22. ECE 331 - Digital Systems Design Concurrent signal assignment conditional signal assignment selected signal assignment Sequential signal assignment if-then-else case for loop Statements

23. ECE 331 - Digital Systems Design The Process Statement • The process statement is used to define an algorithm. • The process, or algorithm, is composed of a set of sequential statements. • The sequential statements and their order define the algorithm. • All process statements execute concurrently. • A process statement has a sensitivity list.

24. ECE 331 - Digital Systems Design Operators

25. ECE 331 - Digital Systems Design Synthesis • A design can be synthesized using any of the architecture models. • However, one model may be more optimal than another, depending on the criteria and constraints of the design. • Regardless of the model used, a netlist is generated in the synthesis process. • The netlist is then “programmed” into a PLD to realize the design.

26. ECE 331 - Digital Systems Design Basic Conventions • VHDL is case insensitive. • It is a free-format language. • Allows spacing for readability • All statements must end with a semicolon. • Comments start with “--” and continue to the end of the line.

27. ECE 331 - Digital Systems Design Basic Conventions • All names and labels should start with a letter. • They should contain only alphanumeric characters and the underscore. • Should not have 2 consecutive underscores. • Should not end with an underscore. • All names and labels should be unique • within a given entity and architecture.

28. ECE 331 - Digital Systems Design Basic Conventions • Filename should match entity name. • Only one entity per file. • There may be more than one architecture for each entity. • However, only one architecture may be associated with an entity at any point in time.

29. ECE 331 - Digital Systems Design A simple logic circuit Example A B C A B F C A B C

30. ECE 331 - Digital Systems Design Signal Assignment signal-name <= expression [after delay]; Can be a signal or a port.

31. ECE 331 - Digital Systems Design Conditional Signal Assignment signal-name <= expression1 when condition1 else expression2 when condition2 else expression3 when condition3 … ; [after delay] can be included after each of the expressions

32. ECE 331 - Digital Systems Design Selected Signal Assignment with expression select signal-name <= expression1 when choice1, expression2 when choice2, ... expressionN whenothers; [after delay] can be included after each of the expressions

33. ECE 331 - Digital Systems Design A B C A B F C A B C Example: A simple logic circuit Entity Architecture

34. ECE 331 - Digital Systems Design Example: Entity

35. ECE 331 - Digital Systems Design Example: Architecture #1 Behavioral Model

36. ECE 331 - Digital Systems Design Example: Architecture #2 Behavioral Model

37. ECE 331 - Digital Systems Design Example: Architecture #3

38. ECE 331 - Digital Systems Design Example: Architecture #3 (cont.) Structural Model

39. ECE 331 - Digital Systems Design Arithmetic Operations on Standard Logic Vectors The basic IEEE standards do not define arithmetic operations for bit_vectors or std_logic_vectors. The package IEEE.Std_logic_unsigned defines arithmetic operations on std_logic_vectors. The arithmetic operators (+, −, and *) and comparison operators (<, <=, =, /=, >=, >) defined in this package treat std_logic_vectors as unsigned binary numbers. These operators are referred to as overloaded operations. This means that the compiler will automatically use the proper definition of the operator depending on its context.

40. ECE 331 - Digital Systems Design Questions?