Combinational Logic Design IV (Design Considerations)

1. Combinational Logic Design IV (Design Considerations) EMT 251 Introduction to IC Design

2. Outline Review Voltage Transfer Characteristic (VTC) Fan In and Fan Out Transistor Sizing Logical Effort Logic Style

3. Review

4. Review 1: Design Abstraction Levels SYSTEM CIRCUIT MODULE DEVICE GATE

5. Review: The MOS Transistor

6. Review: The MOS Transistor (3D)

7. CMOS inverter with load & Characteristic • The voltage transfer characteristic (VTC) gives the response of the inverter circuit, Vout, to specific input voltages, Vin. Fig 1: Inverter with load Fig 2: Inverter with load characteristic

8. Ideal & Typical CMOS Inverter VTC Fig 4: Typical CMOS Inverter VTC Fig 3: Ideal CMOS Inverter VTC

9. Fan-In & Fan Out

10. Elmore Delay Example

11. Fan-In Considerations • Distributed RC model (Elmore delay) • tpHL= 0.69 [R1C1+(R1+R2)C2+(R1+R2+R3)C3+(R1+R2+R3+R4)CL] • tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) • Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case. Note: Too much fan will increase delay

12. tp as a Function of Fan-In Fan in > 4 Gates with a fan-in greater than 4 should be avoided. (more delay)

13. Influence of Fan-In and Fan-Out on Delay • Fan-out: Number of Gates connected to the output • in static CMOS, there are two gate capacitances per Fan-out • Fan-in: Number of independent variables for the logic function, which has a quadratic effect on tp due to: • resistance increasing • capacitance increasing

14. Stages and Fan-in Considerations • Improved Logic Design

15. Alternative logic structures • F = A•B•C•D•E•F•G•H

16. Transistor sizing

17. Transistor sizing • Transistor sizing • as long as fan-out capacitance dominates • Progressive sizing:

18. Relative Transistor Sizing • When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to • maximize the noise margins and • obtain symmetrical characteristics

19. Input re-ordering • when not all inputs arrive at the same time

20. Sizing and Ordering Effects • Progressive sizing in pull-down chain gives up to a 23% improvement. • Input ordering saves 5% • critical path A – 23%

21. Reducing the voltage swing • linear reduction in delay • also reduces power consumption

22. Design techniques for Reduced Voltages • Reduce voltage! • Recent years have seen an acceleration in supply voltage reduction • Design at very low voltages still open question

23. Dynamic Power Consumption • Need to reduce CL , VDD , and f to reduce power. • Power Dissipation is data dependent function of switching activity.

24. Switching Activity • Suppose the system clock frequency = f • Let fsw = αf, where α = activity factor » If the signal is a clock, α = 1 » If the signal switches once per cycle, α = ½ » Dynamic gates: • Switch either 0 or 2 times per cycle, α = ½ » Static gates: • Depends on design, but typically α = 0.1 Dynamic power:

25. Logical Effort

26. Logical Effort (g) • Logical Effort is a ratio of input capacitance of gate to input capacitance of normal skew inverter with same drive strength. • For inverters, we set the fanout of each gate to be identical. • For arbitrary gates, we set the gain of each gate to be identical, where gain is the fanout times “logical effort.”

27. Logical Effort (g) • Logical effort is the compensating factor of how much more input capacitance the gate presents compared to an inverter; it is defined as the ratio of the input capacitance of a gate to the input capacitance of a normal skew inverter with the same drive strength. • Gain and fanout are identical for an inverter because inverters have a logical effort of 1 by definition.

28. Logical Effort (g) • Logical effort is a method to make these decisions • Uses a simple model of delay • Allows back-of-the-envelope calculations • Helps make rapid comparisons between alternatives • Emphasizes remarkable symmetries

29. Logical Effort (g) • Definition: Logical effort, g is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. • Measure from delay vs. fanout plots • Or estimate by counting transistor widths inverter nand nor

30. Logical effort of common gates How to calculate g; Eg: AND gate

31. Example • Logical Effort of building 4 input AND • Two 2 NAND gates is 4/3*4/3 = 1.8 • One 4 NAND is 2 • 2-input NAND/2-input NOR is 4/3*5/3 = 2.2 • Which is best? • Depends on the number of levels of logic you need • If you need lots of gates, 2-input gates are often the best • Using 2-input NAND gates • An 8-input gate will take 6 levels of gates 8 to 4 outputs, 4 to 2 outputs, 2 to 1 output

32. Limits of Logical Effort • Chicken and egg problem • Need path to compute g • But don’t know number of stages without g • Simplistic delay model • Neglects input rise time effects • Interconnect • Iteration required in designs with wire • Maximum speed only • Not minimum area/power for constrained delay

33. Logic style

34. How to Choose a Logic Style • Must consider ease of design, robustness (noise immunity), area, speed, power, system clocking requirements, fan-out, functionality, ease of testing • Current trend is towards an increased use of complementary static CMOS: design support through DA tools, robust, more amenable to voltage scaling. 4-input NAND * Dual Rail

35. CMOS disadvantages • For N-input CMOS gate, 2N transistors required • Each input connects to an NMOS and PMOS transistor • Large input capacitance: limits fan-out • Large fan-in gates: always have long transistor stack in PUN or PDN • Limits pull-up or pull-down delay • Requires very large transistors