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CTL - Redundancy. Discussions – February 28, 2007. Memory Test. Fail Data. Repair Data ATE / BISA. STIL / CTL. Meeting Minutes - 1. Should CTL provide repair data as well? This could imply repair waveforms and provide data Used to describe repair data/mechanism post-analysis.
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Memory Test Fail Data Repair Data ATE / BISA STIL / CTL Meeting Minutes - 1 • Should CTL provide repair data as well? • This could imply repair waveforms and provide data • Used to describe repair data/mechanism post-analysis. • Conclusion : Yes
Repair column for green columns Repair column for blue columns Repair Column Meeting Minutes - 2 • Mechanism to define physical map for redundancy • Memory topology does not define repair columns. • Redundancy may be restricted to specific columns
Meeting Minutes - 3 • Should CTL support repair verification? • Insert fault and then apply repair to verify. • Concluded to be in the domain of behavioral model. CTL cannot be used for verification. • Conclusion : No
Meeting Minutes - 4 • Need mechanism to support fuse-cell within memory. • Would require definition of Power signals as well. • New pin properties / functions.? • PROM (Programmable ROM) • Consists of fuse-cells. • Access Mechanism? Conclusion : need confirmation from memory vendors.
Further Actions • Repair information in CTL • LV design (Saman) • Synopsys design (Slimane)
Repair Type • Internal fuse • electric • External fuse • ECC / EDAC • Correction bits
Repair Access • Serial • Serial data shift • Parallel • Parallel data write • Address map • Word oriented repair
Repair Data • Repairable Rows / Columns • Number of Repairable Rows • Size of row bank • Number of Repairable columns • Size of column bank • Number of repairable bits
Repair Configuration • Fuse Cell Organization • Column address bits • Row address bits • Mapping to physical rows &columns • Offsets.
Internal • Voltage Signals • Must for fuse within memory • Repair register reset • Need to treat differently?