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Pipeline Processor Design Project Jarred Beck

Pipeline Processor Design Project Jarred Beck. Design Assumptions. Three bit opcode This is to be able to address all of the 8k memory directly. 2 13 = 8192 16 registers with some limitations In certain formats, only the first 8 are able to reached

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Pipeline Processor Design Project Jarred Beck

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  1. Pipeline Processor Design Project Jarred Beck

  2. Design Assumptions • Three bit opcode • This is to be able to address all of the 8k memory directly. 213 = 8192 • 16 registers with some limitations • In certain formats, only the first 8 are able to reached • Two reserved registers for the lw and sw.

  3. Design Assumptions Cont. • Pipeline Data Path Structure • Ease of testability. (theoretically) • Fast. • Compiler responsibility’s • Hazard Prevention. • Lw and Sw data moving. • Jump return.

  4. Register List

  5. Instruction Set

  6. Instruction Set Cont.

  7. Control Unit • 11 bits wide. • Controls include • Branch Flags • Jump Flag • Data Memory Read and Write Flags • Register Write Flag • Mux controls for Memory Input, Register Input, and Register Address

  8. Control Unit Cont.

  9. Datapath

  10. Simulation Results • Individual Components • All Components passed tests • Datapath and CPU • Datapath Passed tests • Control Unit Passed test • Memory passed • Top level CPU problems

  11. Moving Forward • Debug Top level VHDL • Altera passes compilation • ModelSim gives error • Synthesize corrected version into board

  12. Questions? The End

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