ENG6090 Reconfigurable Computing Systems

1. ENG6090Reconfigurable ComputingSystems Hardware Description Languages Part 5: Modeling Structure ENG6090 RCS

2. Topics • Describing Structure • Hierarchy • Components, Generics ENG6090 RCS

3. Elements of Structural Models • Structural models describe a digital system as an interconnection of components • Descriptions of the behavior of the components must be independently available as structural or behavioral models • An entity/architecture for each component must be available microphone headphones To processor Micro 3284 speakers amplifier ENG6090 RCS

4. Structural Description • Structural design is the simplest to understand. • This style is the closest to schematic capture and utilizes simple building blocks to compose logic functions. • Components are interconnected in a hierarchical manner. • Structural descriptions may connect simple gates or complex, abstract components. • Structural style is useful when expressing a design that is naturally composed of sub-blocks. ENG6090 RCS

5. Components • During the design of a large application, it is possible • that various parts of the design are in different • stages of completion. • VHDL “component” is a mechanism for specifying • virtual parts (or components). • The top level design can then be described to be • constructed of “virtual” components. ENG6090 RCS

6. Component declaration • A component is declared inside an architecture or • package. • component_decl <= • componentidis • [ generic( generic_interface_list ) ; ] • [ port( port_interface_list ) ; ] • end[ component ] [ id ] ; • A component declaration is almost identical to an • entity declaration. ENG6090 RCS

7. Component instantiation • A component is instantiated inside the architecture • body as a concurrent statement. • component_instantiation_stmt <= • instantiation_label : • [ component ]component_name • [ genericmap ( generic_association_list ) ; ] • [ portmap ( port_association_list ) ; ] • A component label is necessary to identify the • component instance. ENG6090 RCS

8. Modeling Structure: Example • Define the components used in the design • Describe the interconnection of these components s1 HA HA sum In1 s2 In2 c_out c_in s3 a sum a out b carry b ports ENG6090 RCS

9. Modeling Structure • Entity/architecture for half_adder /or_2 must exist library IEEE; use IEEE.std_logic_1164.all; entity full_adder is port (In1, In2, c_in: in std_logic; sum, c_out: out std_logic); end entity full_adder; architecture structural of full_adder is -- Declare all the components used to construct the full adder component hald_adder is -- Declare all the signals used -- Component Instantiation statements i.e. port map() end architecture structural; unique name of the components component type interconnection of the component ports component instantiation statement ENG6090 RCS

10. Modeling Structure • Entity/architecture for half_adder /or_2 must exist architecture structural of full_adder is component half_adder is -- the declaration port (a, b : in std_logic; -- of components you will use sum, carry: out std_logic); end component half_adder; component or_2 is port (a, b : in std_logic; c : out std_logic); end component or_2; signal s1, s2, s3 : std_logic; begin H1: half_adder port map (a => In1, b => In2, sum=>s1, carry=>s3); H2:half_adder port map (a => s1, b => c_in, sum =>sum, carry => s2); O1: or_2 port map (a => s2, b => s3, c => c_out); end architecture structural; unique name of the components component type interconnection of the component ports component instantiation statement ENG6090 RCS

11. A B XOR3 RESULT C Structural Architecture (XOR3 Gate) architecture XOR3_STRUCTURAL of XOR3 is signal U1_OUT:STD_LOGIC; component XOR2 is port( I1 : in STD_LOGIC; I2 : in STD_LOGIC; Y : out STD_LOGIC ); end component; begin U1: XOR2 port map (I1 => A, I2 => B, Y => U1_OUT); U2: XOR2 port map (I1 => U1_OUT, I2 => C, Y => RESULT); end XOR3_STRUCTURAL; ENG6090 RCS

12. Example This Figure Shows a Full Adder Circuit Internal signals ENG6090 RCS

13. Dataflow + Behavior + Structural • First declare and2, xor2 and or3 entities and architectures entity and2 isport ( a,b : in std_logic; c : out std_logic );end and2; architecturedataflowof and2 isbegin c<= a and b; end dataflow; entity or3 isport ( a, b,c : in std_logic; d : out std_logic );end and2; architecturebehaviorof or3 isbegin or3_proc : process isbeginif a = ‘0’ and b = ‘0’ and c=‘0’ then d <= ‘0’; else d <= ‘1’; end if; end process; end behavior; entity xor2 isport ( a,b : in std_logic; c : out std_logic );end xor2; architecturedataflowof and2 isbegin c<= a xor b; end dataflow; ENG6090 RCS

14. Full Adder: Structural Representation • Now use them to implement the full adder • component or3 isport ( a, b,c : in bit; d : out bit );end component; • begin • u0 : xor2 port map ( a, b , w); • u1 : xor2 port map ( w, ci, s ); • u2 : and2 port map ( a, b, x); • u3 : and2 port map ( a, ci, y ); • u4 : and2 port map ( b, ci, z ); • u5 : or2 port map (x,y,z, co); • end struct; entity full_adder is port (a , b , ci: in std_logic; s ,co: out std_logic); end entity; architecture struct of full_adder is --Internal signals signal w,x,y,z : std_logic; --component declaration component and2 port ( a,b : in bit; c : out bit );end component; component xor2 port ( a,b : in bit; c : out bit );end component; ENG6090 RCS

15. External Interface Internal Functionality Register: Structural Rep d0 REG_4 q0 d1 d2 q1 d3 q2 en q3 clk ENG6090 RCS

16. Basic Modeling Concepts External Interface modeled by “entity” VHDL construct. • entity reg4 is • port (do,d1,d2,d3,en,clk : in bit; • qo,q1,q2,q3 : out bit;); • end entity reg4; ENG6090 RCS

17. Structure Example Signals defined at Interface Internal Signal ENG6090 RCS

18. Register: Structure Example • First declare D-latch and and-gate entities and architectures entity d_latch isport ( d, clk : in bit; q : out bit );end entity d_latch; architecture basic of d_latch isbegin latch_behavior : process isbeginif clk = ‘1’ then q <= d after 2 ns;end if;wait on clk, d;end process latch_behavior; end architecture basic; entity and2 isport ( a, b : in bit; y : out bit );end entity and2; architecture basic of and2 isbegin and2_behavior : process isbegin y <= a and b after 2 ns;wait on a, b;end process and2_behavior; end architecture basic; ENG6090 RCS

19. Internal signal Present directory Entity name Architecture name Register: Structure Example • Now use them to implement a register architecture struct of reg4 is signal int_clk : bit; begin bit0 : entity work.d_latch(basic)port map ( d0, int_clk, q0 ); bit1 : entity work.d_latch(basic)port map ( d1, int_clk, q1 ); bit2 : entity work.d_latch(basic)port map ( d2, int_clk, q2 ); bit3 : entity work.d_latch(basic)port map ( d3, int_clk, q3 ); gate : entity work.and2(basic)port map ( en, clk, int_clk ); end architecture struct; ENG6090 RCS

20. Hierarchy and Abstraction • Structural descriptions can be nested • The half adder may itself be a structural model architecture structural of half_adder is component xor2 is port (a, b : in std_logic; c : out std_logic); end component xor2; component and2 is port (a, b : in std_logic; c : out std_logic); end component and2; begin EX1: xor2 port map (a => a, b => b, c => sum); AND1: and2 port map (a=> a, b=> b, c=> carry); end architecture structural; ENG6090 RCS

21. Hierarchy and Abstraction -- top level • Nested structural descriptions to produce hierarchical models • The hierarchy is flattened prior to simulation • Behavioral models of components at the bottom level must exist full_adder.vhd half_adder.vhd or_2.vhd -- bottom level and2.vhd xor2.vhd ENG6090 RCS

22. Hierarchy and Abstraction • Use of IP cores and vendor libraries • Simulations can be at varying levels of abstraction for individual components ENG6090 RCS

23. Generics: Motivations • Oftentimes we want to be able to specify a property separately for each instance of a component. • VHDL allows models to be parameterized with generics. • Allows one to make general models instead of making specific models for many different configurations of inputs, outputs, and timing information. • Information passed into a design description from its environment. ENG6090 RCS

24. Generics • Enables the construction of parameterized models library IEEE; use IEEE.std_logic_1164.all; entity xor2 is generic (gate_delay : Time:= 2 ns); port(In1, In2 : in std_logic; z : out std_logic); end entity xor2; architecture behavioral of xor2 is begin z <= (In1 xor In2) after gate_delay; end architecture behavioral; ENG6090 RCS

25. Generics in Hierarchical Models • Parameter values are passed through the hierarchy architecture generic_delay of half_adder is component xor2 generic (gate_delay: Time); port (a, b : in std_logic; c : out std_logic); end component; component and2 generic (gate_delay: Time); port (a, b : in std_logic; c : out std_logic); end component; begin EX1: xor2 generic map (gate_delay => 6 ns) port map (a => a, b => b, c => sum); A1: and2 generic map (gate_delay => 3 ns) port map (a=> a, b=> b, c=> carry); end architecture generic_delay; ENG6090 RCS

26. Generics: Properties • Generics are constant objects and can only be read • The values of generics must be known at compile time • They are a part of the interface specification but do not have a physical interpretation • Use of generics is not limited to “delay like” parameters and are in fact a very powerful structuring mechanism Design Entity VHDL Program signal signal signal value value ENG6090 RCS

27. Example: N-Input Gate • Map the generics to create different size OR gates entity generic_or is generic (n: positive:=2); port (in1 : in std_logic_vector ((n-1) downto 0); z : out std_logic); end entity generic_or; architecture behavioral of generic_or is begin process (in1) is variable sum : std_logic:= ‘0’; begin sum := ‘0’; -- on an input signal transition sum must be reset for i in 0 to (n-1) loop sum := sum or in1(i); end loop; z <= sum; end process; end architecture behavioral; ENG6090 RCS

28. Example: Using Generic N-Input OR • Full adder model can be modified to use the generic OR gate model via the generic map () construct • Analogy with macros architecture structural of full_adder is component generic_or generic (n: positive); port (in1 : in std_logic_vector ((n-1) downto 0); z : out std_logic); end component; ... ... -- remainder of the declarative region from earlier example ... begin H1: half_adder port map (a => In1, b => In2, sum=>s1, carry=>s3); H2:half_adder port map (a => s1, b => c_in, sum =>sum, carry => s2); O1: generic_or genericmap (n => 2) port map (a => s2, b => s3, c => c_out); end structural; ENG6090 RCS

29. Example: N-bit Register • Used in the same manner as the generic OR gate entity generic_reg is generic (n: positive:=2); port ( clk, reset, enable : in std_logic; d : in std_logic_vector (n-1 downto 0); q : out std_logic_vector (n-1 downto 0)); end entity generic_reg; architecture behavioral of generic_reg is begin reg_process: process (clk, reset) begin if reset = ‘1’ then q <= (others => ‘0’); elsif (rising_edge(clk)) then if enable = ‘1’ then q <= d; end if; end process reg_process; end architecture behavioral; ENG6090 RCS

30. The Generate Statement • What if we need to instantiate a large number of components in a regular pattern? • Need conciseness of description • Iteration construct for instantiating components! • The generate statement • A parameterized approach to describing the regular interconnection of components a: for i in 1 to 6 generate a1: one_bit generic map (gate_delay) port map(in1=>in1(i), in2=> in2(i), cin=>carry_vector(i-1), result=>result(i), cout=>carry_vector(i), opcode=>opcode); end generate; ENG6090 RCS

31. Generate Statement: Example library IEEE; use IEEE.std_logic_1164.all; entity multi_bit_generate is generic(gate_delay:time:= 1 ns; width:natural:=8); -- the default is a 8-bit ALU port( in1 : in std_logic_vector(width-1 downto 0); in2 : in std_logic_vector(width-1 downto 0); result : out std_logic_vector(width-1 downto 0); opcode : in std_logic_vector(1 downto 0); cin : in std_logic; cout : out std_logic); end entity multi_bit_generate; architecture behavioral of multi_bit_generate is component one_bit is -- declare the single bit ALU generic (gate_delay:time); port (in1, in2, cin : in std_logic; result, cout : out std_logic; opcode: in std_logic_vector (1 downto 0)); endcomponent one_bit; signal carry_vector: std_logic_vector(width-2 downto 0); -- the set of signals for the ripple carry begin a0: one_bit generic map (gate_delay) -- instantiate ALU for bit position 0 port map (in1=>in1(0), in2=>in2(0), result=>result(0), cin=>cin, opcode=>opcode, cout=>carry_vector(0)); a2to6: for i in 1 to width-2 generate -- generate instantiations for bit positions 2-6 a1: one_bit generic map (gate_delay) port map(in1=>in1(i), in2=> in2(i), cin=>carry_vector(i-1), result=>result(i), cout=>carry_vector(i),opcode=>opcode); end generate; a7: one_bit generic map (gate_delay) -- instantiate ALU for bit position 7 port map (in1=>in1(width-1), in2=>in2(width-1), result=> result(width-1), cin=>carry_vector(width-2), opcode=>opcode, cout=>cout); end architecture behavioral; ENG6090 RCS

32. Summary • The structural domain is a style in which components are described in terms of interconnection of more primitive components. • Structural design style is the closest to schematic capture and utilizes simple building blocks to compose logic functions. • The VHDL language provides the ability to construct parameterized models using the concept of generics which is a powerful modeling technique to construct standardized libraries of models that can be shared. ENG6090 RCS

33. Extra Slides ENG6090 RCS

34. Generate Statement: Example • Instantiating interconnected components • Declare local signals used for the interconnect • Instantiating an register entity dregister is port ( d : in std_logic_vector(7 downto 0); q : out std_logic_vector(7 downto 0); clk : in std_logic); end entity dregisters architecture behavioral of dregister is begin d: for i in dreg’range generate reg: dff port map( (d=>d(i), q=>q(i), clk=>clk); end generate; end architecture register; ENG6090 RCS