Lecture 19 MOS Amplifier Design

Lecture 19MOS Amplifier Design Michael L. Bushnell CAIP Center and WINLAB ECE Dept., Rutgers U., Piscataway, NJ • Comparison of MOS and bipolar amps • Current sources • MOS single stage amplifiers • Various amplifier types • Summary Analog and Low-Power Design Lecture 19 (c) 2003

MOS Vs. Bipolar Amps MOS Lower transconductance Higher differential offsets in differential amps Infinite input impedance Zero offset as switch Stores signal voltage on monolithic C – senses continuously and non-destructively On-chip sample & hold Bipolar Finite input impedance Cannot do that Analog and Low-Power Design Lecture 19 (c) 2003

Equations Cox W 2L • Id1 = mn (Vgs1 – Vt)2 • ID2 = mn (Vgs2 – Vt)2 • DVi = Vi1 – Vi2 • Id = common mode current • DId = differential current • Solve quadratic to get: DId = mn (DVi) Cox W 2L Cox W 2L 2 Iss mn (Cox W / 2L) - (DVi)2 Analog and Low-Power Design Lecture 19 (c) 2003

Concluding Equations • Id = Id1 + Id2 2 • DId = Id1 – Id2 • Correct only if both transistors saturated • DV • Limiting input behavior when an input exceeds a value • Excursion causing cutoff -- function of: device size, bias current • Behaves like bipolar emitter coupled pair with degeneration resistors • Select to give desired I/P voltage range ISS mn (Cox W / 2L) Analog and Low-Power Design Lecture 19 (c) 2003

Differential I/P Voltage to Turn Off One Transistor • 2 (Vgs – Vt) value when balanced • Increase input range by: • Increasing bias current • Increasing L • Decreasing W • Usually operate with (Vgs – Vt) at several hundred mV Analog and Low-Power Design Lecture 19 (c) 2003

Transconductance ) d DId d DVi | ( • Gm = • Gm = Iss (mn Cox W / L) = gm1 = gm2 • NOT independent of device size, as in bipolar case DVi = 0 ( ( d DIdmn Cox W 2 Iss - DVi2 d DVi 2L mn (Cox W / 2L) ) ) = ( ) - mn Cox W DVi2 2L 2Iss - (DVi)2 mn (Cox W / 2L)) ( ) Analog and Low-Power Design Lecture 19 (c) 2003

Input Offset Voltages • Due to mismatches in: • Load resistor value • Transistor W/L ratios • Vt’s • VOS = VGS1 - VGS2 = Vt1 + 2 ID1 mn Cox (W/L)1 -- Vt2 – 2 ID2 mn Cox (W/L)2 ( ) ( ) Analog and Low-Power Design Lecture 19 (c) 2003

Equations • DID = ID1 – ID2 • ID = ID1 + ID2 2 • D (W/L) = (W/L)1 - (W/L)2 • W/L = (W/L)1 + (W/L)2 2 • DVt = Vt1 – Vt2 • Vt = Vt1 + Vt2 2 • DRL = RL1 – RL2 • RL = RL1 + RL2 2 Analog and Low-Power Design Lecture 19 (c) 2003

Differential Input Parameters • VOS = Differential input V needed to make differential output V exactly 0 • ID1 RL1 = ID2 RL2 • Substitute, neglect higher-order terms, get: • VOS = DVt + (VGS – Vt) - DRLD (W/L) 2 RL (W/L) • MOS: Offset scales directly with VGS – Vt • Bipolar: Mismatch terms multiplied by kT/q, usually smaller than VGS – Vt • MOS has higher VOS for same mismatch or process gradient • Mismatch because ratio of bias current to transconductance much lower than for bipolar [ ( ) ) ( ] Analog and Low-Power Design Lecture 19 (c) 2003

Offset Improvement • Operate MOS amp at low VGS • I/gm affects slew rate for class A input stage – transient performance needs will limit I/gm as well • New mismatch peculiar only to MOS: • Vt mismatch gives a constant offset that is bias current independent • Strong function of process cleanliness • Large centroid (common centroid) structures get Vtmismatch distributions with s 2 mV Analog and Low-Power Design Lecture 19 (c) 2003

MOSFET Current Sources • Ratio of reference current to output current set by device W/L ratios • Most accurate ratioing when devices have same L, but different W’s • L varies substantially due to etching variations • Important parameters: • Small-signal output resistance r0 • Voltage range over which output resistance is maintained • Matching of current sources Analog and Low-Power Design Lecture 19 (c) 2003

Equivalent Open-Circuit Voltage VThev ID-Source Value • r0 = ID Leff d Cd VDS ID d VDS • VThev = r0 ID 1 d Cd VA 1 Leff d VDSl • Derivative is f (substrate doping, tox, gate voltage) • Given a process and (VGS – Vt), it is constant, so L determines r0 ( -1 ) -1 ( ) = ( -1 ) = = = Analog and Low-Power Design Lecture 19 (c) 2003

Behavior • M2 stays in saturation as long as VGD < - Vt • Happens as long as VDS > VDSsat (VGS – Vt) • If not true, transistor enters linear (triode) region Analog and Low-Power Design Lecture 19 (c) 2003

Transistor Behavior • Often need higher r0 values & VThev to improve amplifier voltage gain with higher r0 • Cascode current source can achieve this • M2 shields M1 from voltage variations at O/P terminal: R0 = r02 (1 + gm2 r01) (12.29) • Increases r0, VThev by (1 + gm2 r01) factor • Get VThev of several thousand V Analog and Low-Power Design Lecture 19 (c) 2003

Accounting for Body Effect • ix is test current source • ix flows in r01, so Vsb2 = ix r01 • vgs for dependent sources is – ix r01, • vx = S voltages across r01 & r02 = ix r01 + r02 (ix + gm2 (ix r01) + gmb2 (ix r01)) • vx R0 r01 1 + (gm2 + gmb2) r02 + r02 ix r01 • R0 = r02 (1 + (gm2 + gmb2) r01) + r01 • Body effect of M2 slightly increases R0 ( ) = = Analog and Low-Power Design Lecture 19 (c) 2003

Bipolar Vs. MOS Current Source • Bipolar current source – cannot get R0 > b0 r0 2 • Due to base current in cascode transistor • MOS – can get arbitrarily high impedances with more stacked cascode devices Analog and Low-Power Design Lecture 19 (c) 2003

Cascode Current Source Problems • Serious drawback of stacked devices: • Range of voltage swing at output node where both transistors are saturated is smaller than for simple current source • Minimum V across current source to saturate both devices: (Vt + 2 VDSSat) • Make VDSSat small: • Use large W values in M1 & M2 • Bias transistors at low current • However, Vt represents significant loss of voltage swing Analog and Low-Power Design Lecture 19 (c) 2003

Method • Reduce W/L of M4 by a factor of 4 to compensate for (VGS – Vt) of M5 • Now, need only have 2 VDSSat to saturate both devices • However, MOSFETs have indistinct transitions from triode to saturation regions • Must increase M1 drain voltage several hundred mV to get desired R0 (Eqn. 12.29) Analog and Low-Power Design Lecture 19 (c) 2003

Mathematics • For large Vt, drain of M3 is higher than drain of M2 by > 1 V • Gives a large drain current mismatch between M2 & M3 due to finite device output resistance • Therefore, need M4 as follows to equalize drain voltages Analog and Low-Power Design Lecture 19 (c) 2003

Transistor Mismatch Effects • Mismatch in transistor pairs in current sources • Determines offset voltage of differential amplifiers with current source loads • Limits accuracy of digital-analog converters (DACs) • Fig 4.52 Analog and Low-Power Design Lecture 19 (c) 2003

Assume Mismatched Transistors (W/L)1 • ID1 = mn Cox (VGS – Vt1)2 2 • ID2 = mn Cox (VGS – Vt2)2 2 • Using average and difference equations: ID = ID1 + ID2 ; DID = ID1 – ID2 2 • W (W/L)1 + (W/L)2 L 2 • DW W W L L L • Vt = Vt1 + Vt2 ; DVt = Vt1 – Vt2 2 (W/L)2 = ( ) ( ) - = 1 2 Analog and Low-Power Design Lecture 19 (c) 2003

Mismatch Results • Leads to: DID = - 2 DVt I (VGS – Vt) • Mismatch components: • Geometry dependent, fractional current mismatch independent of bias • Dependent on Vtmismatch, increases as (VGS – Vt) reduces • Fixed threshold mismatch progressively becomes a larger fraction of the total gate drive Analog and Low-Power Design Lecture 19 (c) 2003

Mismatch Problem • Vt has a significant gradient with distance across the wafer: • Must bias current sources from the same bias line when they are physically far apart • Large % errors result in current source outputs if widely separated devices have small (VGS – Vt) Analog and Low-Power Design Lecture 19 (c) 2003

MOS Single-Stage Amplifiers • Poly or diffused R’s have low R , so they must be large when designed as an amplifier load • Instead, use a MOSFET as the passive amplifier load • Common source amp with enhancement-mode load • Fig 4.22 a Analog and Low-Power Design Lecture 19 (c) 2003

Mathematical Analysis • When Vi < 1 Vt, M1 is off – no current flow • When Vi > 1 Vt, M1 turns on, M1 & M2 saturate • Effective Z: Seen looking into source terminal of load • Roughly 1 /gm • Same calculation as for Bipolar emitter follower Analog and Low-Power Design Lecture 19 (c) 2003

Mathematics • Apply known vx to output • v1 = - vx rp (voltage divider) rp + RS • ix = vx + gm vx rp rp + Rs rp + Rs • 1 = 1 + gm rp = 1 + gm rp R0 rp + Rs rp + Rs rp + Rs • b0 = gm rp • R0 = vx = rp + Rs 1 + Rs ix 1 + b0 gm 1 + b0 ( ) ( ) ( ) ( ) Analog and Low-Power Design Lecture 19 (c) 2003

Lecture 19 MOS Amplifier Design