1 / 8

CSC Muon Sorter Status Tests Plans M.Matveev August 21, 2003

CSC Muon Sorter Status Tests Plans M.Matveev August 21, 2003. Muon Sorter Board. Status. • Have one assembled MS board with a mezzanine FPGA • Three other boards have been assembled and partially tested without mezzanines • Have a dedicated test stand

Download Presentation

CSC Muon Sorter Status Tests Plans M.Matveev August 21, 2003

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. CSC Muon Sorter Status Tests Plans M.Matveev August 21, 2003

  2. Muon Sorter Board

  3. Status • Have one assembled MS board with a mezzanine FPGA • Three other boards have been assembled and partially tested without mezzanines • Have a dedicated test stand - 9U crate with Track Finder Backplane - MS with mezzanine FPGA - Clock and Control Board - SBS 620 VME controller - Linux PC

  4. Hardware/Firmware Tests • VME Access to FPGA and JTAG controller was checked. • Extensive tests of sorting logic and LUTs • Front panel connection to GMT was verified with a loopback cable FPGA

  5. VME/JTAG Interface XILINX PARALLEL CABLE TDI TCK TMS Xilinx XC2V4000 mezzanine FPGA and associated EPROM’s may be loaded/programmed from: • Xilinx Parallel Cable IV • Fairchild SCANPSC100F JTAG controller under VME control MUX FAIRCHILD SCANPSC100 TDO XILINX FPGA XILINX PLD VME National Semiconductor provides a free software to operate SCANPSC100F controller, that was adopted by UF to work via VME using SBS 620 Master. • We have successfully run this software to program 4 EPROM’s residing on the mezzanine card • Program time is ~1 min (~4 min over Xilinx Parallel Cable IV)

  6. FPGA Latency F=45 Mhz

  7. Tests with Sector Processor For initial tests we need one Sector Processor with mezzanine FPGA installed and minimal firmware: • Output 512*32 memory buffer for data to be sent to MS • Input 512*2 memory buffer for “winner” bits from MS Memory buffers can be either FIFO’s or dual-port RAM’s. Both must be under VME control. Verilog implementation of the dual-port RAM can be borrowed from the TMB design and adopted for SP.

  8. Plans Continue bench testing when SP is available • Data consistency check • Winner logic • Latency Tests with Global Muon Trigger Integrated test of the peripheral/TF electronics

More Related