CSC Trigger Status, MPC and Sorter

1. CSC Trigger Status, MPC and Sorter B. Paul Padley Rice University November 2003

2. CSC Muon Trigger Scheme EMU Trigger On-Chamber Trigger Primitives Muon Port Card(Rice) 3-D Track-Finding and Measurement Trigger Motherboard(UCLA) Strip FE cards Sector Receiver/ Processor(U. Florida) LCT OPTICAL FE SP SR/SP MPC LCT TMB 3 / port card FE 2 / chamber 3 / sector Wire LCT card Wire FE cards In counting house RIM CSC Muon Sorter(Rice) RPC Interface Module RPC DT 4 4 4 Global L1 Global  Trigger 4

3. MPC Block Diagram MPC Block Diagram Rice 9U x 400 MM BOARD VME J1 CONNECTOR VME INTERFACE UCLA MEZZANINE CARD (XCV600E) CCB CCB INTERFACE SORTING LOGIC INPUT ANDOUTPUT FIFO CCB TMB_1 OPTO SER TMB_2 CUSTOM PERIPHERAL BACKPLANE 3 OPTICAL CABLES TO SECTOR PROCESSOR TMB_3 OPTO SER TMB_4 TMB_5 TMB_6 OPTO SER TMB_7 FINISAR FTRJ-8519-1-2.5 OPTICAL TRANSCEIVERS TMB_8 TLK2501 SERIALIZERS FPGA TMB_9 SN74GTLP18612 GTLP TRANSCEIVERS

4. Muon Port Card Rice VME Interface (glue logic) GTLP Receivers TLK2501 serializers Optomodules Mezzanine card

5. MPC Design Status Rice • 3 boards were fabricated and assembled in summer 2002 • Tested MPC standalone (sorter logic) and with one and two Trigger Motherboards and full-size custom backplane

6. UCLA Cosmic Ray Test Cosmic Ray tests were performed at UCLA in preparation for time structured test beam during spring 2003

7. Beam Test With 2 CSC’s at X5a /

8. Beam Test Setup TTC crate Trigger primitives DAQ Data PC FED crate 1 DDU Track Finder Crate Peripheral Crate 2 DMB, 2 TMB 1 CCB, 1 MPC TRIDAS • 2 CSC’s, all on-chamber boards • Up to 80K events read out in 2.6s spill beam S1 S3 S2 CSC 2 CSC 1

9. CSC Peripheral Crate From front-end cards Clock & Control Board (CCB) with TTCrm Muon Port Card (MPC), which sends trigger primitives on optical links

10. Test Performed • Compare • MPC output LCTs stored in FIFO on MPC • TMB output LCTs extracted from DDU data • List of checks • Bit errors in data transmission • Data acceptance from 2 TMBs • Sending MPC winner bit to TMB • Sorting of LCTs based on “Quality Bits”

11. Results from summer beam test • During time structured beam in the summer the set of tests were repeated successfully • Note this was using clock distribution from TTCmi->TTCvi->TTCrm on CCB • Existing TTCrm adequate for Intracrate functionality. Also adequate for DAQ path (which uses crystal oscillators to clock links since they are asynchronous) • However, MPC->SP communication failed. • TTC Jitter one of the problems.

12. TTC QPLL Mezzanine card • Three made available to CSC group for testing during Sept.03 structured beam test • Provides stable clock signalsat 40, 80, and 160 MHz at correct LHC frequency • Installed on Clock and Control Board (CCB) with 40 MHz clean clock sent to backplane and 80 MHz clock sent by twisted pair to SP and MPC • Noticed that CCB commands have 1 BX extra latency with TTCRq TTCRq

13. PLL Results • Using either the home-built VCXO+PLL solution or the CERN QPLL solution for the 80 MHz reference clock to TLK2501 receivers: • PLL locks to incoming machine clock • Measured frequency: 40.078893(1) MHz • No errors on optical links reported over many hours of PRBS and data tests • Data successfully logged by both CSC DAQ and CSC Track-Finder readout • SP data FIFO synchronized to L1A

14. TTCRq (QPLL) Test Results • QPLL 80 MHz clock directly to MPC transmitters & home-built VCXO+PLL for SP receivers: • No link errors for 20 minute PRBS test • QPLL 80 MHz clock directly to SP receivers andMPC uses default clock multiplier: • No link errors for 15 minute PRBS test • Successfully logged data for 10K events (run 5151) • QPLL 40 MHz clock on TF crate backplaneand SP uses DLL in FPGA for clock multiplier: • Solution tried for Phase 1 (May) structured beam running • Link errors observed in PRBS test • TTCRq on CCB in peripheral crate • Able to take data with same trigger efficiency (i.e. TTCRq works for peripheral crate electronics as well and is compatible with TTCRm)

15. Results from Sept Beam test • Intracrate tests successfully repeated • This time PLL patch was used to stabilize clocking of optical links in the trigger path • MPC to SP communication now successful • Last day of run got hold of TTCrq an again the test was successful.

16. Muon Sorter Block Diagram Rice VME J1 CONNECTOR 9U * 400 MM BOARD VME & JTAG INTERFACE SN75LVDS387 DRIVERS 68-pin CONNECTORS CCB INTERFACE SORTER LOGIC INPUT AND OUTPUT FIFO SP1 SP2 SP3 SHIELDED TWISTED PAIR CABLES TO GMT CRATE SP4 CUSTOM BACKPLANE SP5 SP6 SP7 SP8 SP9 SP10 MEZZANINE CARD VIRTEX XC2V4000 SP11 SP12 GTLP TRANSCEIVERS

17. Muon Sorter VME/JTAG INTERFACE MEZZANINE CARD LVDS DRIVERS AND SCSI-3 CONNECTORS GTLP BACKPLANE INTERFACE

18. Trackfinder crate at Rice Sector Processor CCB Sorter

19. FPGA Design • Comprises: - Sorter “4 out of 36” based on 7-bit Rank - Output LUT - Input and output FIFO buffers for testing purposes - “Winner” logic - CCB interface - VME interface (A24D16 slave + Geographical Address) • Based on Xilinx XC2V4000-5FF1152C, common mezzanine card with the Sector Processor • Latency – 135 ns

20. Muon Sorter Status and Plans • Have 4 boards in hand, one is stuffed (except backplane interface) • Have a dedicated Wiener 9U crate with VME J1 backplane and custom • Track Finder backplane installed • Sector Processor – to – MS interface test currently underway

21. Milestones Rice Sep-02 Prototype construction: • MPC done, • CCB done • waiting for new TTCrq, and will then redo • As a result of TTCrx Jitter problem need resdesign with TTcrq • Muon Sorter Done

22. More Milestones • Apr-03 Prototype testing done: Underway • Sep-03 Final designs done • MPC significantly delayed (until summer ’04) • Although MPC prototype was completed summer ’02, integration testing of it will not be completed until spring ‘04 • Oct-04 Production done • At risk given the final design schedule • Apr-05 Installation done