Minimum Implant Area-Aware Gate Sizing and Placement

1. Minimum Implant Area-Aware Gate Sizing and Placement Andrew B. Kahng and Hyein Lee UC San Diego VLSI CAD Laboratory

2. Outline • Minimum Implant Area Constraint • Motivation • Prior Work • Minimum Implant Area-Aware Placement and Sizing • Experimental Results • Conclusions and Future Work

3. Minimum Implant Area (MinIA) Constraint • Implant (active) layers • Regions for ion implantation (= Vt) • Same as the entire cell regionin most cases • Limitation of optical lithography (at λ=193nm) • Cannot make small patterns • Minimum implant area constraint ⇒ A small island of implant layer is not allowed ⇒ Challenge for physical design in sub-22nm nodes Minimum implant width constraint <Standard cell layout> L H L Implant area for P, NMOS Violation

4. Motivation: MinIA Constraint in Sub-22nm Nodes • MUST consider neighbor cells’ size and Vt type • New physical design problems: placement and sizing Minimum cell size < MinIA constraint Minimum cell size > MinIAconstraint MinIA constraint L H L L H L NOW: Violation In sub-22nm nodes WAS: OK In previous nodes

5. Motivation: MinIA-Aware Placement and Sizing • Traditional placement and sizing are separate problems • Placement problem: Place each cell without overlap • Gate sizing problem: Select size and Vt of each cell to minimize power under timing/design constraints • MinIA-aware placement and sizing ⇒ No longer independent of each other in sub-22nm nodes • Sizing needs to understand placement • Example: Changing Vt can create MinIA violations depending on the placement • Placement, sizing and MinIA constraints MUST be considered together L L L H L L

6. Our Work • Redefine the traditional placement and gate sizing problems to capture new placement, sizing and MinIArule interaction • Propose placement and sizing heuristics to optimize power under the MinIA constraint • Our proposed methods are implemented in C++ and incorporated into a standard P&R flow • Our placement heuristic fixes almost all of violations while commercial tools cannot fix up to 64% of violations • Our sizing and placement heuristic achieves comparable power reduction to the conventional sizing approach without creating MinIA violations

7. Prior Work: Literature • Gate sizing, and co-optimization with placement • Method to minimize power and ECO cost • Sequential optimization of placement and sizing • Linear (1-D) placement • Graph model-based approach • Dynamic programming • Layout effect-aware placement • STI stress-aware placement • No work considers the MinIA rules in placement and/or sizing

8. Prior Work: Commercial P&R Tools • Case study of P&R tools • Technology: 45nm technology with modified MinIArules • Commercial P&R tools fix MinIA violations by inserting filler cells • Result of two commercial tools • Commercial tools cannot fix all of MinIA violations 50% remaining violations

9. Outline • Minimum Implant Area Constraint • Motivation • Prior Work • Minimum Implant Area-Aware Placement and Sizing • Experimental Results • Conclusions and Future Work

10. Problem Formulation • Problem: MinIA-aware sizing and placement • Minimize power • Subject to: • Minimum implant area constraints • Timing constraints (slack, transition time) • No overlap in placement • Sizing and placement are performed sequentially

11. Sequential Optimization • We perform sizing and placement sequentially in our optimization • Three combinations of sizing and placement problems • Free sizing and MinIA-aware placement • Allow MinIA violations and fix the violations later • StrictMinIA-aware sizing • Do not allow any MinIA violations during sizing • RelaxedMinIA-aware sizing and MinIA-aware placement • Allow fixable MinIA violations • Used for our optimizer

12. How to Fix MinIA Violations? • Levers to solve MinIA violations Violation We must make the blue area larger than MinIA constraint (dashed red box) L H L L L L H L L H H <Move neighbor cells> <Downsize neighbor cells> L L L L <Change Vt of cells>

13. Our Heuristic Flow: Placement timing check is needed Calculate whitespace for violating cells Move neighbor cells to obtain spacing Insert same Vt filler cells around violating cells Insert filler cells #Vio= 0? #Vio= 0? finish finish Y Y N N Vt swap the violating cell/ its neighbor cells to match Vt Downsize neighbor cells to obtain spacing Insert filler cells #Vio= 0? finish Y N finish

14. Our Heuristic Flow: Sizing and Placement Calculate sensitivity Sensitivity function = ∆leakage/∆TNS • TNS = total negative slack • ∆TNS is calculated considering sizing and MinIA costs Fixable? discard N Y Add the cell to the candidate list Pick the most promising cell And commit Fix MinIA violations Revert Timing feasible? Y N

15. Our Optimizer P&R Design (DEF)/LEF min implant layer rules geometry info MinIAOpt def/lef2oa Timer Tool/ P&R Tool (DB update, ECO sizing/ placement/ routing) OADB MinIA Violation Check Tcl socket Apply solutions MinIA-Aware Placement/Sizing Timing update save P&R Design Final P&R Design

16. Outline • Minimum Implant Area Constraint • Motivation • Prior Work • Minimum Implant Area-Aware Placement and Sizing • Experimental Results • Conclusions and Future Work

17. Experimental Setup • Technology: 45nm technology with modified MinIA rules • Testcases • dma, mpeg, aesand jpegfrom OpenCore • High utilization (75~82%) is used • Many small cells are used (% of minimum size cells : 59~84%) • Additional testcases (aes_var*) with different Vt cell distributions • Various minimum implant width constraints

18. Experimental Results: Placement • How much MinIA violations can be fixed by our placement heuristic? • Placement results with Const3 • Our approach fixes almost all of violations while commercial tools cannot fix up to 64% of violations 64% vs. 3%

19. Experimental Results: Sizing and Placement • Which sizing heuristics show good results w.r.t. both power reduction and MinIA constraints? • Comparison results between the three heuristics • Our sizing heuristic (3) does not increase MinIAviolations while maintaining low leakage power F (1) Best leakage reduction (1) Many MinIA violations (2) Worst leakage reduction (2) Some MinIA violations (3) Small MinIA violations (3) Good leakage reduction

20. Conclusion • We address new gate sizing and placement problems arising in sub-22nm VLSI due to MinIA constraint • We propose a heuristic sizing and placement method considering MinIA • Our placement heuristic fixes almost all of violations while commercial tools cannot fix up to 64% of violations • Our sizing and placement heuristic achieves comparable power reduction without creating MinIA violations

21. Future Work • Single-row placement with MinIA fixing by using dynamic programming • Unified placement, sizing and Vt-swap heuristics • Multi-row placement consideration MinIA violations H L H L Standard cell row1 L H L Standard cell row2

22. Thank you!