Robust Gate Sizing by Geometric Programming

1. Robust Gate Sizing by Geometric Programming Jaskirat Singh, Vidyasagar Nookala, Tom Luo, Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota

2. Outline • Introduction • Motivation • Robust gate sizing • Impact of variations on the conventional gate sizing solution • Uncertainty ellipsoid • Robust GP formulation • Experimental results • Summary

3. delay specs # of chips delay Introduction There’s many a slip between the cup and the lip • Impact of increasing variability in design Process uncertainties Environment variations Tool inaccuracies What you draw ………… is NOT what you get!! • Timing yield of the circuit affected

4. 1 3 2 Gate Sizing Problem Minimize Area (Power) Subject to: Delay ≤ Dspec Xmin ≤ X ≤ Xmax • Previous work • Fishburn and Dunlop, ICCAD ’85 • Sapatnekar et. al, TCAD ’93 • Chen et. al, TCAD’99 A number of dies have to die!! • Do not account for variations • Circuit optimized for a specified delay

5. Robust Gate Sizing Solutions delay specs new delay specs original • Traditional worst-casing techniques • Set tighter specs than required • May lead to large overheads # of chips • Corner based designs • Design for extreme values of the parameter variations • Ignores correlations betweenrandom variables • Curse of dimensionality delay slack • Statistical Designs pmin ≤ p ≤ pmax

6. Outline • Introduction • Motivation • Robust gate sizing • Impact of variations on the conventional gate sizing solution • Uncertainty ellipsoid • Robust GP formulation • Experimental results • Summary

7. R CL C CL Conventional Gate Sizing Solution Min Area (W, L) Subject to: Delay (W, L) ≤ Dspec Wmin ≤W ≤ Wmax L=Lmin Area, Delay are posynomials in (W, L) Posynomial delay models, e.g., Elmore delay - Replace each gate by RC elements Delay constraints at the output of each gate: Solve the GP by convex optimization tools

8. (W0,L0) An example of Gaussian variations in (W, L) varies as Impact of Variations on Gate Sizing Parametric variations as random variable (W, L) vary as (W0+δW, L0+δL) Effect on delay constraints and constraint function Define Using first order Taylor series Nominal term Variation term Delay constraints : Nominal term + Variation term ≤ ti Violations if: Variation term > Slack

9. Outline • Introduction • Motivation • Robust gate sizing • Impact of variations on the conventional gate sizing solution • Uncertainty ellipsoid • Robust GP formulation • Experimental results • Summary

10. x An ellipse set b x0 a y0 y Uncertainty Ellipsoid Model x An ellipsoid set z y Substituting

11. eig2 eig1 x0 Uncertainty Ellipsoid Model • Ellipsoid uncertainty model • Bounded model for random variations :random variations nominal design covariance matrix

12. Outline • Introduction • Motivation • Robust gate sizing • Impact of variations on the conventional gate sizing solution • Uncertainty ellipsoid • Robust GP formulation • Experimental results • Summary

13. Robust Gate Sizing Procedure • Generate posynomial delay constraints by STA • Use Elmore delay for simplicity • Any generalized posynomial constraints may be used • Kasamsetty, Ketkar and Sapatnekar, TCAD’98. Using first order Taylor series for variations around nominal values Nominal term Variation term

14. eig2 eig1 x0 Robust Gate Sizing Procedure • Nominal term + Variation term ≤ ti • Use the ellipsoid uncertainty model • For robustness • Nominal term + Max δXєU(Variation term) ≤ti This is still a posynomial An example follows

15. (W1 , L1 ) (W2 , L2 ) 1 2 CL Example Convert each original posynomial constraint to a set of posynomial robust constraints

16. (W1 , L1 ) (W2 , L2 ) 1 2 CL Example First order Taylor series approximation

17. (W1 , L1 ) (W2 , L2 ) 1 2 CL Example

18. (W1 , L1 ) (W2 , L2 ) 1 2 eig2 eig1 x0 CL Example Use uncertainty ellipsoid model Using Cauchy Schwartz inequality

19. CL Example (W1 , L1 ) (W2 , L2 ) 1 2 Define robust variables r1, r2 A set of posynomialrobust constraints P : covariance matrix Pij ≥ 0

20. GP Method • Convert each original constraint to a set of robust constraints • Cost of at most two additional variables per constraint

21. The Complete Procedure Generate Elmore delay based constraints by STA Taylor series expansion of constraint functions Model variations as an uncertainty ellipsoid Generate robust constraints Solve the GP

22. Experimental Setup • ISCAS’85 benchmark circuits optimized • 20% L, 25%W 3σ variations assumed • Tspec set as 15% slack point • MOSEK solver for the GP • Monte Carlo simulations for timing yield determination • 5000 samples drawn assuming multivariate normal N(X0 ,P) • Non-robust designs compared with robust designs

23. Results Monte Carlo simulations for timing yield determination A comparison of robust and non-robust sizing solutions

24. Summary • Propose a novel uncertainty aware gate sizing scheme • Use an uncertainty ellipsoid to model random variations • Robust formulation relaxed to a GP • Timing yield of robust circuits improves 3-4 times • Better than the conventional worst-casing method