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EE Design Status D Cockerill CERN 19 July 2006

EE Design Status D Cockerill CERN 19 July 2006. PATCH PANELS. ENVIRONMENTAL SHIELD. ECAL EE End Cap components. SUPPORT RING. SUPERCRYSTALS THIS FACE. BACKPLATE. ECAL EE End Cap Build – Layout. SUPPORT RING. BACKPLATE. ~3.6m. VFE ELECTRONICS. MODERATOR. END CAP DEE. SIDE VIEW.

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EE Design Status D Cockerill CERN 19 July 2006

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  1. EE Design Status D Cockerill CERN 19 July 2006

  2. PATCH PANELS ENVIRONMENTAL SHIELD ECAL EE End Cap components SUPPORT RING SUPERCRYSTALS THIS FACE BACKPLATE

  3. ECAL EE End Cap Build – Layout SUPPORT RING BACKPLATE ~3.6m VFE ELECTRONICS MODERATOR END CAP DEE SIDE VIEW

  4. ECAL End Cap Build - Layers Arrangement at the Rear of the End Cap Backplate Backplate Cooling, fitting of patch panels, FOM Protection plates, HV support End Cap inner Shielding, Front Moderator Protection plates, LV support Mechatronics Support plates Umbilical connection, VFE Mothercards/support frames, LV distribution Mechtronics cooling system, internal flow and return manifolds VFE, LV and FE cards attachment, Inner Moderator Data/trigger fibre boxes plus support Rear Moderator, closure of End Cap

  5. Backplate Cooling, fitting of patch panels, FOM Backplate cooling All 4 backplates have their associated cooling pipes However these pipes must be fitted to the patch panels and ring flange exit points to the (non existant) blocks for the quick disconnect fittings Design/fabrication of blocks Mario Mounting Jose

  6. Backplate Cooling, fitting of patch panels, FOM Cooling completion Blocks for quick disconnect fittings mounted on patch panels and ring flanges Pipes cut to suit (use of CERN gases division?) Fit pipes to backplate and to blocks Dismount pipes Apply thermal compound to cooling plates Remount pipes, secure to blocks Leak tests

  7. Backplate Cooling, fitting of patch panels, FOM Patch panels Have to be redesigned and remade due to the new manifold design for the electronics cooling bars The ‘plane’ of cooling is 20mm lower (nearer to backplate) than before Design John Manufacture Mario? Fitting Jose

  8. Backplate Cooling, fitting of patch panels, FOM Fibre Optic monitoring The new laser layout has been incorporated by Saclay, new mounting drawings produced Updated locations for the diffusing spheres. Dees are mirrors of each other on an Endcap Additional mounting holes on backplate, according to Dee location in CMS Holes completed for all 4 Dees by Jose

  9. Backplate Cooling, fitting of patch panels, FOM VPT stability pulser One Patch Panel location per Dee for LED array and associated electronics Must serve 18 L1 diffusers Allocated volume only 4cm x 15cm x 4.5cm Design RAL/UVa RISK: Is volume enough ??

  10. EndCap EE All large mechanical pieces are at CERN Dry assembly of env. screen produced in Russia

  11. EE: VPT production & gluing, Supercrystals EE VPT to crystal gluing 2800 VPTs shipped from UK to CERNAll tested upon receipt by Russia - INR Up to 50 EE crystals/VPTs glued each week110 of current EE crystal stock (~350 xtals) done First “Russian” SC completed in June 2006built using CRISTAL database

  12. EE electronics SC HV cards105 pre-production cards completed All R & C components for EE delivered Motherboards2 prototypes on Dee4 600 cards by end 2006 EE VFE cardsRC feedback on MGPA tuned for EEInput diode for VPT spark protection30 prototypes produced in Feb 06250 cards now under test 3130 cards by end July 06FE cards80pre-production cards tested 800 cards produced by Sep 2006 Preliminary results, ~ 3900 e- per channelCross talk < 0.1%Meets EE requirements

  13. EE trigger Pseudostrip (5 crystal) allocationsEE+ towards I.P Consequent trigger towers (TCC level)EE+ towards I.P

  14. EE : preparing for the assembly Ensuring correct cabling of the channels LED cabling tester from UVa Trigger map (H.Heath)

  15. EE data and trigger readout The fibre readout fan-out boxes (two layers) serving the EE DCCs and TCCs in the control room 900 readout fibres to correctly route per Dee

  16. “Dee4” project EE assembly has started “Dee4” will provide crucial assembly and test beam insights Dee1 assembly from September 2006 “Dee4”First large scale test of integration philosophy 20 SCs mounted on BP Dee4 by end 2006 Trigger mapping at motherboard 10 cooling blocks, main manifold “Dee4” to testbeam in May 2007

  17. EE Planning CMS windowfor Dee1end Sep 07 EE+mid Jan 08 EE-mid Mar 08 • Dee 1 End Sep 2007Dee 2 End Dec 2007Dee 3 Mid Mar 2008Dee 4 Mid Apr 2008

  18. EE planning Crucial to introduce as much parallel assembly and integration as possibleQuality control at each crucial step Suggestion to carry out all SC mounting and Dee assembly in bldg 867 This offers many very attractive features - all major activities under one roof - proximity of expert teams - realisation of the EE trigger, from motherboard level to fibre readout level - multiple DAQ test systems, needed for EE QA, available locally - cooling capacity for one entire Dee - LV power Crystal Palace Advance preparation of all large mechanics - Dees into OPAL frames - dry assembly tests of Environmental screens - BP cooling installation - Mounting laser monitoring system

  19. EE - Conclusions EE assembly has started Much progress with the EE large mechanics, VPTs, SC assembly, electronics, and trigger and data mapping “Dee4” will provide crucial assembly and test beam insights Dee1 assembly from September 2006 We are on the learning curve for EE assembly

  20. Additional info follows, next slide

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