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Extended Burst Mode Design

Extended Burst Mode Design. Orignally Submitted by : Amish Patel amishjpa@usc.edu. Revised by : Sumit Bhargava sumitbha@usc.edu. Introduction. Illustrate example on Extended Burst Mode Design. Topics of Discussion. Extended Burst Mode Specification

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Extended Burst Mode Design

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  1. Extended Burst Mode Design Orignally Submitted by : Amish Patel amishjpa@usc.edu Revised by : Sumit Bhargava sumitbha@usc.edu EE552 Extra Credit Project

  2. Introduction • Illustrate example on Extended Burst Mode Design EE552 Extra Credit Project

  3. Topics of Discussion • Extended Burst Mode Specification • Hazard-free Next State Logic Synthesis • 3D Automatic Synthesis Algorithm EE552 Extra Credit Project

  4. Extended Burst ModeSpecification • All input transitions in input burst should change in assigned time d  Circuit settle with in time e  Output burst generated • Arrivals of input transitions in input burst may be arbitrary order. • Restrictions: Maximal Set property Unique Entry Condition EE552 Extra Credit Project

  5. Restrictions • Maximal set property --- to prevent non-deterministic state transitions 0 0 a+c+/x+ c+/x+ a-/ a-/ Correct Implementation ? 3 1 3 1 c-/x- a+c-/x- ? If c goes lower first in state 1  arbitrary decision to wait for b+ (go to state 2) or go to state 3 b+c-/y+ b+c-/y+ 2 2 Illegal implementation Legal implementation a, b and c are input variables, x and y are output variables + represents rising transition - represents falling transition EE552 Extra Credit Project

  6. Restrictions (Contd.) • Unique entry condition abcxy=00001 0 abc/xy = 000/01 0 b+c*/x+ b+c*/x+ Correct 1 { 01x11 } 1 { 010/11,011/11 } a-c*/x+y+ a+c+/y- a-/x+y+ a+c+/y- {11000} {01011} 2 3 2 3 c-/x- c-/x- Unique Not Unique EE552 Extra Credit Project

  7. 3D Machine Operation Three protocols / modes of operation • Mode I : input burst  output and sstate bursts simultaneously • Mode II: input burst  output burst  sstate burst We will be using this mode in rest of presentation • Mode III : input burst  sstate burst  output burst differ in timing of burst of variable change EE552 Extra Credit Project

  8. * = Directed Don’t Care ? This symbol is used to model concurrent input /output transitions Variable is allowed to change before it is required. The input variable is allowed to change with output and state variable Eg. a+ b* / x- b+ / x+ 1 2 3 Here we allow input variable b to change while going from state 1 to state 2 but state 2 does not care about value of b, but it is in state 3 that we require b to be high. Input variable b is changing all across going from state 1 to state 3 concurrently with output and state variable. EE552 Extra Credit Project

  9. Example Mode II: input burst  output burst  sstate burst Mode III : input burst  sstate burst  output burst b+c+/x- a-b-/x- a+b*/x+y+ c-/x+y- 0 1 2 3 abc/xy=000/00 abc/xy = 111/01 abc/xy=1*0/11 abc/xy=110/10 EE552 Extra Credit Project

  10. Conflict during Table Construction Mode II Machine b+c+/x- a-b-/x- a+b*/x+y+ c-/x+y- 0 1 2 3 abc/xy=000/00 abc/xy = 111/01 abc/xy=110/10 abc/xy=1*0/11 a = 0 a = 1 bc bc xy 00 01 11 10 00 01 11 10 xy 00 00 0 01 01 2 11 11 1 1 10 10 10 Conflict EE552 Extra Credit Project

  11. Next-state Table (before layer encoding) a = 0 a = 1 bc bc xy 00 01 11 10 xy 00 01 11 10 00 00 0 01 01 Layer A Mode III Machine 11 11 1 1 10 10 a = 0 a = 1 bc bc xy 00 01 11 10 xy 00 01 11 10 00 00 01 01 Layer B 2 11 11 10 10 3 EE552 Extra Credit Project

  12. Next-state Table (after layer encoding) a = 0 a = 1 bc bc xy 00 01 11 10 xy 00 01 11 10 00 00 0 01 01 q = 0 11 11 Mode II Machine 1 1 10 10 a = 0 a = 1 bc bc xy 00 01 11 10 xy 00 01 11 10 00 00 01 q = 1 01 2 11 11 10 10 3 EE552 Extra Credit Project

  13. Conflict during Table Construction Mode III Machine b+c+/x- a-b-/x- a+b*/x+y+ c-/x+y- 0 1 2 3 abc/xy=000/00 abc/xy = 111/01 abc/xy=1*0/11 abc/xy=110/10 abc xy 000 001 011 010 101 100 110 111 00 0 01 2 11 1 1 10 10 Conflict EE552 Extra Credit Project

  14. Next-state Table (before layer encoding) a = 0 a = 1 bc bc 00 01 11 10 xy 00 01 11 10 00 00 0 01 01 Layer A 11 11 1 1 10 10 Mode III Machine a = 0 a = 1 bc bc 00 01 11 10 xy 00 01 11 10 00 00 01 01 Layer B 2 11 11 10 10 3 EE552 Extra Credit Project

  15. Next-state Table (after layer encoding) a = 0 a = 1 bc bc xy 00 01 11 10 xy 00 01 11 10 00 00 0 01 01 q = 0 11 11 Mode III Machine 1 1 10 10 a = 0 a = 1 bc bc xy 00 01 11 10 xy 00 01 11 10 00 00 01 q = 1 01 2 11 11 10 10 3 EE552 Extra Credit Project

  16. Automatic SynthesisProcedure • Next State Assignment • Layer Minimization • Layer Encoding • Combinational logic synthesis EE552 Extra Credit Project

  17. Another Example c-/y- c-/x- 2 0 1 <d+>c+/x+ <d->c+/y+ If d sampled at rising edge of clock c is 1, x follows the clock and rises to 1,y=0; Otherwise, y follows clock and x=0 EE552 Extra Credit Project

  18. Example Specification c-/y- c-/x- 2 0 1 <d->c+/y+ <d+>c+/x+ dc dc xy xy 01 11 10 01 11 10 00 00 00 00 01 10 00 00 0 0 1 0 a 0 0 01 00 01 01 00 01 0 0 0 0 2 c 11 11 10 00 10 10 00 10 0 1 1 0 1 K-map for x Next State Table EE552 Extra Credit Project

  19. State Graph d=1 d=0 c+ c+ x+ 1 d- d+ 2 c- c- 3 After x+ and d = 1, machine waits in 1, d may fall freely, leading to 2. If next input is d+ c-, machine may change from 213, giving output as 1-0-1-0 which is a dynamic hazard EE552 Extra Credit Project

  20. Modified State GraphAfter Adding a New Layer d=1 d=0 c+ c+ p+ x+ Solution: Add new layer and to move to it via a state burst before enabling i/p to change if next i/p is unconditional and enables o/p to fall d- d+ c- c- EE552 Extra Credit Project

  21. Partial Next-State Table p=0 p=1 dc dc xy 01 11 10 01 11 10 00 00 xy 00 00 00 00 00 00 00 10 10 00 0 0 01 01 11 11 10 00 00 10 00 10 10 00 1 EE552 Extra Credit Project

  22. Partial K-map dc dc xy 01 11 10 xy 01 11 10 00 00 00 0 0 0 0 00 0 1 1 0 01 01 11 11 10 0 0 10 0 1 1 0 EE552 Extra Credit Project

  23. Partial K-map fornext p dc dc xy 01 11 10 xy 01 11 10 00 00 00 0 0 1 0 00 0 1 1 0 01 01 11 11 10 0 0 10 0 1 1 0 EE552 Extra Credit Project

  24. References • Synthesis of Asynchronous Controllers for Heterogeneous Systems, Kenneth Yun, Ph.D Dissertation 1994 • Automatic Synthesis of Extended Burst Mode Circuits:Part I-II, Kenneth Yun,David Dill • EE552- Fall 2001 Lectures and Discussions EE552 Extra Credit Project

  25. Policy "I alone revised this project. I received no help from anyone else. This material is not copied or paraphrased from any other source except where specifically indicated. I grant my permission for this project to be placed on the course homepage during future semesters. I understand that I could receive an F for the course retroactively, even after graduation, if this work is later found to be plagiarized.“ Submitted by Sumit Bhargava EE552 Extra Credit Project

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