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Studies on Single DC link Fed Multilevel Inverter Topologies Using Flying Capacitor And Floating

This presentation provides an overview of multilevel inverters and explores various topologies, advantages, and fields of research. It focuses on a proposed five-level inverter topology using cascading flying capacitor inverter and H-Bridge. The presentation includes circuit diagrams, voltage states, and PWM generation techniques.

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Studies on Single DC link Fed Multilevel Inverter Topologies Using Flying Capacitor And Floating

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  1. Studies on Single DC link Fed Multilevel Inverter Topologies Using Flying Capacitor And Floating Capacitor Fed H-Bridges P. Roshan Kumar Research Supervisor: Prof. K. Gopakumar DESE, IISc, Bangalore DESE, Indian Institute of Science Bangalore

  2. Overview of Presentation • Overview of multilevel inverters • Five level inverter topology • Common mode voltage eliminated three level inverter • Seventeen-level inverter topology • Back to back connected multilevel inverter DESE, Indian Institute of Science Bangalore

  3. Multilevel inverters • Applications in medium and high voltage drives above 1kV • Reliable operation of devices beyond 1200V are not practical with two level inverters • Voltage balancing of devices in a series connection is very difficult • Need transformers to generate higher voltages from a low voltage inverter hence extra cost DESE, Indian Institute of Science Bangalore

  4. Advantages of Multilevel inverters • The voltage waveforms are close to sinusoid • Reduced harmonics distortion • Reduced filtering requirements • Reduced current ripple • Reduced heating of magnetics and capacitors • Lower switching frequencies of devices • Reduced switching losses (Distributed losses) • Reduced EMI DESE, Indian Institute of Science Bangalore

  5. Fields of Research in Multilevel inverters • Reliable topologies • Ease of control and reduced complexity • Stability of the output voltage level • Optimized number of active and passive devices • Modularity of the systems DESE, Indian Institute of Science Bangalore

  6. Part I A Five Level Inverter Topology With Single DC-Supply By Cascading Flying Capacitor Inverter and H-Bridge DESE, Indian Institute of Science Bangalore

  7. Proposed Five-level Inverter One phase Schematic • Possible voltage levels. • 0 • Vdc/4 • Vdc/2 • 3Vdc/4 • Vdc O DESE, Indian Institute of Science Bangalore

  8. State for Voltage level 0 • State ( 0, 0, 0, 0 ) • C1 : No effect • C2 : No effect I O DESE, Indian Institute of Science Bangalore

  9. Redundant States for pole voltage of VDC/4 • State ( 0, 0, 0, 1 ) • C1 : No effect • C2 : Discharge I O • State ( 0, 1, 1, 0 ) • C1 : Discharge • C2 : Charge I O • State ( 1, 0, 1, 0 ) • C1 : Charge • C2 : Charge I O DESE, Indian Institute of Science Bangalore

  10. Redundant States for pole voltage of VDC/4 DESE, Indian Institute of Science Bangalore

  11. Redundant States for pole voltage of VDC/2 • State ( 1, 0, 0, 0 ) • C1 : Charge • C2 : No effect I O • State ( 0, 1, 0, 0 ) • C1 : Discharge • C2 : No effect I O DESE, Indian Institute of Science Bangalore

  12. Redundant States for pole voltage of 3VDC/4 • State ( 0, 1, 0, 1 ) • C1 : Discharge • C2 : Discharge I O • State ( 1, 0, 0, 1 ) • C1 : Charge • C2 : Discharge I O • State ( 1, 1, 1, 0 ) • C1 : No Effect • C2 : Charge I O DESE, Indian Institute of Science Bangalore

  13. Redundant States for pole voltage of VDC • State ( 1, 1, 1, 1 ) • C1 : No effect • C2 : No effect I O DESE, Indian Institute of Science Bangalore

  14. Three phase Circuit Diagram DESE, Indian Institute of Science Bangalore

  15. Possible Space Vector voltage states • Voltage levels in A phase 0 3Vdc/4 Vdc Vdc/2 Vdc/4 DESE, Indian Institute of Science Bangalore

  16. Possible Space Vector voltage states • Voltage levels in A and B Phases DESE, Indian Institute of Science Bangalore

  17. Possible Space Vector voltage states • Voltage levels in A, B and C Phases DESE, Indian Institute of Science Bangalore

  18. Five Level Three Phase Space Vector Polygon Sector-I DESE, Indian Institute of Science Bangalore

  19. Sector-I (60 degree) Voltage States and Redundancies Voltage Ref • 0: 0 • 1: Vdc/4 • 2: Vdc/2 • 3: 3Vdc/4 • 4: Vdc DESE, Indian Institute of Science Bangalore

  20. Controller block diagram • Level shifted carrier based PWM is used to generate the three phase voltage. • Controller was realized using TMS320F2812 DSP along with SPARTAN-3 XC3S200 FPGA to generate all the 48 PWM signals. • All the capacitor voltage levels are sensed and compared with reference values using hysteresis comparator • 3-Phase Y-connected 400V, 50Hz, SCIM is run in open loop V/f algorithm. DESE, Indian Institute of Science Bangalore

  21. PWM generation for multilevel inverters the reference wave before and after the addition of the common-mode voltage and the four level shifted carriers (b) the reference waveform after translating into the innermost carrier region. DESE, Indian Institute of Science Bangalore

  22. Level shifted carrier based PWM VDC 3VDC/4 VDC/2 VDC/4 0 VDC/4 0 the reference wave before and after the addition of the common-mode voltage and the four level shifted carriers (b) the reference waveform after translating into the innermost carrier region. DESE, Indian Institute of Science Bangalore

  23. Experimental Setup and Results • A 3KW,400V 50Hz, Induction machine is run in V/f Mode • Level- shifted carrier based SV-PWM algorithm is implemented on TMS320F2812 DSP and Xilinx SPARTAN-3 XC3S200 FPGA • Dead time of 3 µS • Motor is run at various modulation indices • MI = 0.2 at 10Hz • MI = 0.4 at 20Hz • MI = 0.6 at 30Hz • MI = 0.8 at 40Hz • Sudden acceleration to test the capacitor balancing algorithm • Capacitor balancing algorithm is disabled and re enabled to see the response of the controller DESE, Indian Institute of Science Bangalore

  24. Phase and Pole Voltage for 10 Hz • V AN: Phase Voltage (50V/div) • IA : Phase Current (2A/div) • VC1: Cap1 Voltage Ripple (5V/div) • VC2: Cap2 Voltage Ripple (10V/div) • Time scale: 20mS/div • V A0: Pole Voltage (50V/div) • IA : Phase Current (2A/div) • VC1: Cap1 Voltage Ripple (5V/div) • VC2: Cap2 Voltage Ripple (10V/div) • Time scale: 20mS/div DESE, Indian Institute of Science Bangalore

  25. Phase and Pole Voltage for 20 Hz • V AN: Phase Voltage (100V/div) • IA : Phase Current (2A/div) • VC1: Cap1 Voltage Ripple (5V/div) • VC2: Cap2 Voltage Ripple (10V/div) • Time scale: 10mS/div • V A0: Pole Voltage (100V/div) • IA : Phase Current (2A/div) • VC1: Cap1 Voltage Ripple (5V/div) • VC2: Cap2 Voltage Ripple (10V/div) • Time scale: 10mS/div DESE, Indian Institute of Science Bangalore

  26. Phase and Pole Voltage for 30 Hz • V AN: Phase Voltage (100V/div) • IA : Phase Current (2A/div) • VC1: Cap1 Voltage Ripple (5V/div) • VC2: Cap2 Voltage Ripple (10V/div) • Time scale: 10mS/div • V A0: Pole Voltage (100V/div) • IA : Phase Current (2A/div) • VC1: Cap1 Voltage Ripple (5V/div) • VC2: Cap2 Voltage Ripple (10V/div) • Time scale: 10mS/div DESE, Indian Institute of Science Bangalore

  27. Phase and Pole Voltage for 40 Hz • V AN: Phase Voltage (100V/div) • IA : Phase Current (2A/div) • VC1: Cap1 Voltage Ripple (5V/div) • VC2: Cap2 Voltage Ripple (10V/div) • Time scale: 5mS/div • V A0: Pole Voltage (100V/div) • IA : Phase Current (2A/div) • VC1: Cap1 Voltage Ripple (5V/div) • VC2: Cap2 Voltage Ripple (10V/div) • Time scale: 5mS/div DESE, Indian Institute of Science Bangalore

  28. Capacitor Voltage under sudden acceleration • The motor is accelerated from 10Hz to 40Hz at no load and the capacitor voltages are almost constant in this duration • V AN: Phase Voltage (200V/div) • IA : Phase Current (2A/div) • VC1: Cap1 DC Voltage (200V/div) • VC2: Cap2 DC Voltage (50V/div) • Time scale: 1S/div DESE, Indian Institute of Science Bangalore

  29. Capacitor Balancing Algorithm Test • The Capacitor balancing algorithm has been disabled for C1 and C2 at T1, enabled for C1 at T2 and C2 at T3. • V AN: Phase Voltage (200V/div) • IA : Phase Current (2A/div) • VC1: Cap1 DC Voltage (200V/div) • VC2: Cap2 DC Voltage (50V/div) • Time scale: 2S/div DESE, Indian Institute of Science Bangalore

  30. Component Comparison With Standard Inverters • NPC : Neutral Point Clamped Inverter • FC : Flying Capacitor Inverter • CHB : Cascaded H-Bridge Inverter • PI : Proposed Inverter Configuration DESE, Indian Institute of Science Bangalore

  31. Reliable Operation • In case of device failures in H-Bridge, the configuration can work as 3 level inverter at full power rating at all modulation indices there by improving the fault operability of the configuration • S3 or S4 open fault • S3`or S4` short fault • S3 or S4 short fault • S3`or S4` open fault DESE, Indian Institute of Science Bangalore

  32. Conclusion • A novel five-level inverter with single DC link has been proposed, analyzed and implemented in hardware. • The performance of the inverter is tested by running a three phase induction motor at no load and the voltages and currents are analyzed both during steady state and during transients at various modulation indices and frequencies. • Use if single DC supply enables back to back connection where multiple sources and loads can interact over single DC link. • Important feature is fault tolerant reliable operation at full load. If one of H-Bridges fail, the inverter can still be operated at full load by bypassing the faulty h bridge and operating the inverter as a three-level inverter. DESE, Indian Institute of Science Bangalore

  33. Part II Common-Mode Voltage Eliminated Three-Level Inverter using a Three-Level Flying Capacitor Inverter and Cascaded H-Bridge DESE, Indian Institute of Science Bangalore

  34. Three Level Inverter with Zero Common Mode Voltage • The common mode voltage of the induction motor connected in single ended configuration is given by VCM = (VA + VB+ VC)/3 DESE, Indian Institute of Science Bangalore

  35. Five Level Three Phase Space Vector Polygon Sector-I DESE, Indian Institute of Science Bangalore

  36. Sector-I (60 degree) Voltage States and Redundancies Voltage Ref • -2 : -Vdc/2 • -1 : -Vdc/4 • 0 : 0 • 1: Vdc/4 • 2: Vdc/2 DESE, Indian Institute of Science Bangalore

  37. 5-Level States with zero common mode voltage • Values of (a, b, c) • -2 = -Vdc/2 • -1 = -Vdc/4 • 0 = 0 • 1 = Vdc/4 • 2 = Vdc/2 DESE, Indian Institute of Science Bangalore

  38. Location of States with Zero Common mode Voltage DESE, Indian Institute of Science Bangalore

  39. Location of States with Zero Common mode Voltage DESE, Indian Institute of Science Bangalore

  40. Location of States with Zero Common mode Voltage DESE, Indian Institute of Science Bangalore

  41. Experimental Setup and Results • A 3KW,400V 50Hz, Induction machine is run in V/f Mode • Level- shifted carrier based SV-PWM algorithm is implemented on TMS320F2812 DSP and Xilinx SPARTAN-3 XC3S200 FPGA • Dead time of 3 µS • Motor is run at various modulation indices • MI = 0.2 at 10Hz • MI = 0.4 at 20Hz • MI = 0.6 at 30Hz • MI = 0.8 at 40Hz • Sudden acceleration to test the capacitor balancing algorithm • Capacitor balancing algorithm is disabled and re enabled to see the response of the controller DESE, Indian Institute of Science Bangalore

  42. Controller block Diagram DESE, Indian Institute of Science Bangalore

  43. Phase and Pole Voltage for 10 Hz • V AO: Pole Voltage (100V/div) • V AN : Phase Voltage (100V/div) • VNO: Common-mode Voltage (20V/div) • IA: Phase Current (2A/div)Cap2 • Time scale: 20mS/div • V AO: Pole Voltage (100V/div) • VC1: Cap1(Vdc/2) Voltage (50V/div) • VC2: Cap2(Vdc/4) Voltage (50V/div) • IA : Phase Current (2A/div) • Time scale: 20mS/div DESE, Indian Institute of Science Bangalore

  44. Phase and Pole Voltage for 20 Hz • V AO: Pole Voltage (100V/div) • V AN : Phase Voltage (100V/div) • VNO: Common-mode Voltage (20V/div) • IA: Phase Current (2A/div)Cap2 • Time scale: 10mS/div • V AO: Pole Voltage (50V/div) • VC1: Cap1(Vdc/2) Voltage (50V/div) • VC2: Cap2(Vdc/4) Voltage (50V/div) • IA : Phase Current (2A/div) • Time scale: 10mS/div DESE, Indian Institute of Science Bangalore

  45. Phase and Pole Voltage for 30 Hz • V AO: Pole Voltage (100V/div) • V AN : Phase Voltage (100V/div) • VNO: Common-mode Voltage (20V/div) • IA: Phase Current (2A/div)Cap2 • Time scale: 10mS/div • V AO: Pole Voltage (100V/div) • VC1: Cap1(Vdc/2) Voltage (50V/div) • VC2: Cap2(Vdc/4) Voltage (50V/div) • IA : Phase Current (2A/div) • Time scale: 10mS/div DESE, Indian Institute of Science Bangalore

  46. Phase and Pole Voltage for 40 Hz • V AO: Pole Voltage (100V/div) • V AN : Phase Voltage (100V/div) • VNO: Common-mode Voltage (20V/div) • IA: Phase Current (2A/div)Cap2 • Time scale: 5mS/div • V AO: Pole Voltage (100V/div) • VC1: Cap1(Vdc/2) Voltage (10V/div) • VC2: Cap2(Vdc/4) Voltage (50V/div) • IA : Phase Current (2A/div) • Time scale: 5mS/div DESE, Indian Institute of Science Bangalore

  47. Phase and Pole Voltage for 50 Hz • V AO: Pole Voltage (100V/div) • V AN : Phase Voltage (100V/div) • VNO: Common-mode Voltage (20V/div) • IA: Phase Current (2A/div)Cap2 • Time scale: 5mS/div • V AO: Pole Voltage (100V/div) • VC1: Cap1(Vdc/2) Voltage (50V/div) • VC2: Cap2(Vdc/4) Voltage (50V/div) • IA : Phase Current (2A/div) • Time scale: 5mS/div DESE, Indian Institute of Science Bangalore

  48. Capacitor Voltage Under Sudden Acceleration • The motor is accelerated from 10Hz to 40Hz at no load and the capacitor voltages are almost constant in this duration • V AN: Phase Voltage (100V/div) • VC2: Cap2(Vdc/4) Voltage ripple (2V/div) • VCM: Common mode Voltage (10V/div) • IA : Phase Current (2A/div) • Time scale: 500mS/div DESE, Indian Institute of Science Bangalore

  49. Capacitor Balancing Algorithm Test • The Capacitor balancing algorithm has been disabled for C1 and C2 at T1, enabled for C1 at T2 and C2 at T3. • VC1: Cap1(Vdc/2) Voltage (50V/div) • VC2: Cap2(Vdc/4) Voltage (50V/div) • VCM: Common-mode Voltage (10V/div) • IA : Phase Current (10A/div) • Time scale: 500mS/div DESE, Indian Institute of Science Bangalore

  50. Reliable Operation • In case of device failures in H-Bridge, the configuration can work as a normal 3 level inverter at full power rating at all modulation indices there by improving the fault operability of the configuration • S3 or S4 open • S3’or S4’ short • S3 or S4 short • S3’or S4’ open DESE, Indian Institute of Science Bangalore

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