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Flip-Flop J-K

Flip-Flop J-K. Flip-Flop J-K. LATCH RS. Flip-Flop J-K. Análise:. 1o. CASO => J = K = 0 => Q = Qn ; Q_inv = Qn_inv => MANTÉM. LATCH RS. R. S. Flip-Flop J-K. Análise:. 2o. CASO => J = 0; K = 1 =>. Q. R. C. Q_inv. S. Flip-Flop J-K. Análise:. Q = 0.

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Flip-Flop J-K

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  1. Flip-Flop J-K

  2. Flip-Flop J-K LATCH RS

  3. Flip-Flop J-K Análise: 1o. CASO => J = K = 0 => Q = Qn ; Q_inv = Qn_inv => MANTÉM LATCH RS R S

  4. Flip-Flop J-K Análise: 2o. CASO => J = 0; K = 1 =>

  5. Q R C Q_inv S Flip-Flop J-K Análise: Q = 0 2o. CASO => J = 0; K = 1 => Q = 0; Q_inv = 1 RESET LATCH RS Se Q = 0 Vcc Q = 0 Q Se Q = 1 R C Q_inv S

  6. Flip-Flop J-K Análise: Vcc Q = 1 3o. CASO => J = 1; K = 0 => Q = 1; Q_inv = 0 Q R C SET Q_inv S Se Q = 0; Q_inv = 1 LATCH RS Q = 1 Q Se Q = 1; Q_inv = 0 R C Q_inv S

  7. Flip-Flop J-K Análise: Vcc Q = 1 4o. CASO => J = 1; K = 1 => Q = (Qn)’; Q R I N V E R T E C Q_inv S Se Q = 0; Q_inv = 1 LATCH RS Vcc Q = 0 Q Se Q = 1; Q_inv = 0 R C Q_inv S

  8. Flip-Flop J-K Tabela de Transição Q J C Q_inv K Símbolo

  9. library IEEE; use ieee.std_logic_1164.all; use IEEE.std_logic_arith.all; entity ff_jk is port ( j, k, clock, reset_n : in std_logic; q, qinv : out std_logic ); end ff_jk; architecture comportamental of ff_jk is signal qaux : std_logic; begin process (j, k, clock, reset_n) begin if reset_n = '0' then q <= '0'; qinv <= '1'; elsif rising_edge (clock) then if j = '0' and k = '1' then q <= '0'; qaux <= '0'; qinv <= '1'; elsif j = '1' and k = '0' then q <= '1'; qaux <= '1'; qinv <= '0'; elsif j = '1' and k = '1' then q <= not qaux; qinv <= qaux; qaux <= not qaux; end if; end if; end process; end comportamental; Descrição VHDL – Flip- Flop JK com reset assíncrono

  10. Simulação Flip-Flop J-K J = k = 1 RESET Assíncrono Inverte saídas Estado SET Estado RESET

  11. Q J C Q_inv K Q T T C Q_inv Símbolo Flip-Flop tipo T T Tabela de Transição

  12. Descrição VHDL – Flip- Flop T com reset assíncrono library IEEE; use ieee.std_logic_1164.all; use IEEE.std_logic_arith.all; entity ff_t is port ( t, clock, reset_n : in std_logic; q, qinv : out std_logic ); end ff_t; architecture comportamental of ff_t is signal qaux : std_logic; begin process (t, clock, reset_n) begin if reset_n = '0' then q <= '0'; qinv <= '1'; qaux <= '0'; elsif rising_edge (clock) then if t= '1' then q <= not qaux; qaux <= not qaux; qinv <= qaux; end if; end if; end process; end comportamental;

  13. Simulação Flip-Flop Tipo T

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