Reading Assignment: Chapter 3 in Logic and Computer Design Fundamentals, 4 th Edition by Mano

1. Lecture #7 EGR 270 – Fundamentals of Computer Engineering Reading Assignment: Chapter 3 in Logic and Computer Design Fundamentals, 4th Edition by Mano • Combinational Functions and Circuits • Functions and fundamental circuits are introduced in this chapter which are useful in designing larger digital circuits. • These circuits are presented as functional blocks – fundamental, reusable circuits. The focus is to develop the functional blocks such that they are reusable, are easily expanded for use with larger functions, and are efficiently designed for implementing via VHDL programming. • Examples of functional blocks to be introduced: • Decoders • Encoders • Priority encoders • Multiplexers • De-multiplexers • Magnitude Comparators • Programmable Logic (Chapter 6)

2. Lecture #7 EGR 270 – Fundamentals of Computer Engineering Combinational Logic Using MSI and LSI devices Although our focus will be more on defining functional blocks that are designed to be reusable and to be implemented using VHDL, many of these fundamental circuits are also available as commercially available IC’s. Commercial devices can perform complex functions using perhaps a single IC, thus saving space. They are typically faster that equivalent circuits that we might build using discrete logic gates. It might be a good idea to browse through a Logic Data Book to see what is available. A few devices are listed below. Assortment of commercially available combinational logic devices

3. Lecture #7 EGR 270 – Fundamentals of Computer Engineering Decoders An N-bit decoder has 2N outputs, only one of which may be activated at a given time. If the device is active-HIGH , then only one output may be HIGH at any time. If the device is active-LOW , then only one output may be LOW at any time. Example: A 3-bit decoder might also be called a 3-line-to-8-line decoder or a 3x8 decoder. The block diagram is shown below: • Discuss: • basic operation • the truth table

4. Lecture #7 EGR 270 – Fundamentals of Computer Engineering Active-LOW versus Active-HIGH decoders Enable lines – essentially act as ON/OFF switches Example: Show the truth table and block diagram for an active-LOW 2x4 decoder with an enable line, E.

5. Lecture #7 EGR 270 – Fundamentals of Computer Engineering • Circuit Design • Show that decoder outputs are essentially minterms and draw a circuit for: • 1x2 decoder (no enable, active-HIGH outputs) • 2x4 decoder (no enable, active-HIGH outputs) • 3x8 decoder (no enable, active-HIGH outputs) • Note the gate input count on the 2x4 and 3x8 decoder circuits

6. Lecture #7 EGR 270 – Fundamentals of Computer Engineering Decoder expansion using hierarchy The text introduces a procedure for forming any (n x 2n) decoder by expanding smaller decoders. The result requires only 2-input AND gates (rather than n-input) and inverters. This technique is especially useful for building large decoders using reusable fundamental blocks. Figure 3-19 below illustrates a 3x8 decoder constructed using this method:

7. Lecture #7 EGR 270 – Fundamentals of Computer Engineering Implementing Boolean functions using decoders Note that the decoder outputs for active-HIGH decoders are simply minterms, so F = (minterms) = (active-HIGH decoder outputs) Example: Implement f(A,B,C) = (0, 3, 5, 6) using a 3 x 8 decoder with active-HIGH outputs Note that the decoder outputs for active-LOW decoders are simply maxterms, so F = (maxterms) =  (active-LOW decoder outputs) Example: Implement f(A,B,C) = (0, 3, 5, 6) using a 3 x 8 decoder with active-LOW outputs

8. Lecture #7 EGR 270 – Fundamentals of Computer Engineering • Decoder IC’s • 74155 Data Sheet (dual 2x4 decoder/single 3x8 decoder) – see next page • The 74156 is similar to the 74155 except that it has open-collector outputs instead of totem-pole outputs (discuss the advantage of this). • Show how to connect the 74155 as a 2x4 decoder and also as a 3x8 decoder. • Show how to use two 74155’s to form a 4x16 decoder.

9. Lecture #7 EGR 270 – Fundamentals of Computer Engineering

10. Lecture #7 EGR 270 – Fundamentals of Computer Engineering Encoder An encoder is essentially the opposite of a decoder. An N-bit encoder has 2N inputs lines, one of which is active, and N output lines that carry the binary code corresponding to the active input. The 8 x 3 encoder shown below might also be called an octal-to-binary encoder. Example: Show an encoder with sample inputs and outputs.

11. Lecture #7 EGR 270 – Fundamentals of Computer Engineering Note that encoders and decoders perform the opposite functions. Example: Show an 8x3 encoder followed by a 3x8 decoder with some sample inputs and outputs. Example: Show a 3x8 decoder followed by an 8x3 encoder with some sample inputs and outputs.

12. D0 D1 2 2 x D2 8 x 3 1 D3 Output 2 y Encoder D4 Code 0 2 z D5 D6 V V = 1 for a valid code (0 if invalid) D7 Lecture #7 EGR 270 – Fundamentals of Computer Engineering Basic Encoder Design Draw the truth table for an 8x3 encoder. From the truth table, determine expressions for the outputs x, y, and z. Valid Output? One problem with the encoder design above is that there is no way to indicate that an invalid input occurred. This problem can be resolved by using an additional output called a valid line, V.

13. Lecture #7 EGR 270 – Fundamentals of Computer Engineering Decoders and Encoders - Applications Decoders can be used to reduce the number of wires needed to control multiple outputs. Encoders can be used to reduce the number of wires needed to read multiple inputs. These wires might be to external devices or might be within a digital circuit. • Encoder Example 1 – Reading 256 external sensors with a computer • Suppose that a computer was used to read the status of 256 sensors in a special application where only one sensor would ever be HIGH at a given time. • One option would be to find a 256-pin connector to work with the computer (good luck). • A better option would be to use an 256x8 encoder and use an 8-bit connector on the computer. The computer could then simply read the code to determine which sensor was activated. • Encoder Example 2 – Reading a keyboard • Encoders are also used in keyboards. • Rather than send over 100 different signals from the keyboard corresponding to the key that has been pressed, the keys are encoded using an ASCII code. • A 7-bit ASCII code is sufficient to represent all keys along with a 128x7 encoder.

14. 32 x 5 Encoder . . . Lecture #7 EGR 270 – Fundamentals of Computer Engineering Encoder Example 3: IEEE sponsors competitions for students in electrical and computer engineering. In a prior IEEE SouthEastConsoftware competition held at Virginia Tech, Computer Engineering students were given the challenge of designing a piece of Windows-based software to control an HO-scale train. A track was set up with 32 sensors. A sensor would read HIGH when the train was over it and LOW otherwise. A 32x5 encoder was used to encode the sensor information. The train, track, sensors, and encoder were provided and the distance between the sensors was specified. Student teams had to write software to: 1) stop and start the train at any sensor location 2) execute a planned train route 3) display the speed of the train etc.

15. Lecture #7 EGR 270 – Fundamentals of Computer Engineering • Decoder Example: • A few years ago TCC worked with ODU, William & Mary, and Hampton University on the Virginia Student Balloon Launch (VSBL) Program. • NASA sponsors a number of such projects, where NASA engineers provide a high-altitude balloon (up to 100,000 ft) and engineering students at colleges and universities design experiments for the upper atmosphere. • In one experiment William and Mary students provided 8 stainless steel cylinders that were pumped to a vacuum just before liftoff. The valve on each cylinder was opened briefly at precise altitudes so that they would suck in a sample of the air which was analyzed after landing to detect the presence of certain pollutants. • The onboard computer could have tied up 8 output lines to control the 8 cylinders, but instead used a 3x8 decoder and thus only used 3 output lines.

16. Highest priority D7 D6 . . . . 2 2 x D5 8 x 3 1 D4 Output 2 y Priority Encoder D3 Code 0 2 z D2 D1 V V = 1 for a valid code (0 if invalid) Lowest priority D0 Lecture #7 EGR 270 – Fundamentals of Computer Engineering • Priority Encoder • A priority encoder is an encoder where: • more than one input may be activated • each input is assigned a priority • the output code corresponds to the highest priority input that has been activated. Example: Show a priority encoder with several activated inputs

17. Lecture #7 EGR 270 – Fundamentals of Computer Engineering Example: Show the truth table for an 8x3 priority encoder with an output line V with active-HIGH inputs and outputs.

18. Lecture #7 EGR 270 – Fundamentals of Computer Engineering Example: A computer uses “interrupts” to allow peripheral devices, such as modems, printers, disk drives, scanners, cameras, etc., to request attention from the computer. But the computer can only do one task at a time, so they are assigned priorities such as in the table shown below. Discuss using a priority encoder as an “interrupt handler”.

19. Lecture #7 EGR 270 – Fundamentals of Computer Engineering Magnitude Comparators A magnitude comparator is a device that can be used to compare two binary inputs. The output will indicate if the inputs are equal or else which input is the largest. Comparing for equality Exclusive-NOR (equivalence) gates can be used to compare binary values. 1-bit comparison for equality: 4-bit comparison for equality: Two 4-bit words A = A3A2A1A0 and B = B3B2B1B0 are equal if A3 = B3 , A2 = B2 , etc.

20. Lecture #7 EGR 270 – Fundamentals of Computer Engineering Comparing to determine if A > B, A < B, or A = B A typical block diagram for a 4-bit comparator is shown. Algorithm for A > B: . if A3 = 1 and B3 = 0, (A3' B3 ) then A > B . if A3 = B3 (i.e., x3 - see previous page) and A2 = 1 and B2 = 0, (x3A2' B2 ) then A > B . etc. . Develop expressions for A>B and A<B

21. Lecture #7 EGR 270 – Fundamentals of Computer Engineering Diagram for 4-bit comparator based on algorithm’s developed on the last page:

22. Lecture #7 EGR 270 – Fundamentals of Computer Engineering • PSPICE Analysis of Digital Circuits • In EGR 260-261 PSPICE is used to analyze various types of circuits. Several methods of analysis are used, including: • Bias Point Analysis • DC Sweep • AC Sweep • Transient • Parametric • Analysis of logic circuitswill only involve transient analysis - in order to generate timing diagrams to show outputs for various combinations of inputs. • Full version of PSPICE: One of the strengths of the full version of PSPICE is that it includes libraries for tens of thousands of components. • Evaluation version of PSPICE: The evaluation version contains a few hundred devices, most of which are 7400 series TTL devices. This is very useful for this course and allows students to analyze circuits using devices that are pin-for-pin compatible with those covered in the text and in lab.

23. T = 2ms A T = 8ms B T = 4ms C T = 2ms Count (ABC): 0 1 2 3 4 5 6 7 0 Lecture #7 EGR 270 – Fundamentals of Computer Engineering New Parts: The following parts will be introduced: 1) DIGITAL CLOCK – located in the library named SOURCE.OLB Note that the OFFTIME and the ONTIME can be set to produce a waveform with the desired period. For example, the Digital Clock below has a period of 2ms. Similarly, three Digital Clocks could be used to generate waveforms A, B, and C representing the 8 possible input combinations. Since the period of the MSB is 8ms, a transient analysis of 8ms could be used to test circuit outputs for all 8 input combinations.

24. U1A U2A 1 1 3 3 2 2 7400 7400 Lecture #7 EGR 270 – Fundamentals of Computer Engineering 2) HI and LO inputs – located in the library named SOURCE.OLB Note that a ground is not used in digital circuits and HI and LOW inputs must be produced using these inputs (5V and GROUND will not work). 3) 7400 Series TTL devices – located in the library named EVAL.OLB The EVAL library contains a wide assortment of 7400 series devices. In general, they are pin-for-pin compatible with commercially available devices. For simple logic gates, such as the 7400 NAND, 7402 NOR, 7404 NOT, etc., single gates are inserted rather than an entire IC (a 7400 NAND contains 4 2-input NAND’s). More complex devices match the IC’s exactly. Some examples are shown below.

25. Lecture #7 EGR 270 – Fundamentals of Computer Engineering However, changing the letter after the IC number will allow you to use other gates on the same IC. PSPICE will automatically update the pin numbers when the letter is changed. For a more complex device like the 74155 3 x 8 decoder, the parts in PSPICE are pin-for-pin compatible with the IC.

26. Lecture #7 EGR 270 – Fundamentals of Computer Engineering • PSPICE Demonstration: • Implement the function f(A, B, C, D) = (0, 2-4, 9, 13-15) • In SOP form using AND, OR, and NOT gates • In POS form using AND, OR, and NOT gates • Implement the function f(A, B, C) = A’B’ + BC’ + AB using a 74155 ( 3x8 decoder) • In each case above, verify the output by generating a timing diagram showing all inputs, the output, and a bus showing the corresponding minterms. • If inputs A, B, C, and D are used and you want to show the value of ABCD using a bus, • Select Add a Trace • Enter {A,B,C,D};Minterm;D • where A is the MSB, the signals A, B, C, D must be separated by commas or spaces and placed in braces, Minterm is any name for the bus, and D means decimal format (use B for binary, O for octal, H for hexadecimal).