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Differential Signaling

Differential Signaling. Introduction Reading Chapter 6. Agenda. Differential Signaling Definition Voltage Parameters Common mode parameters Differential mode parameters Current mode logic (CML) buffer Relate to parameters Modeling & simulation Timing parameters Clock recovery

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Differential Signaling

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  1. Differential Signaling Introduction Reading Chapter 6

  2. Agenda • Differential Signaling Definition • Voltage Parameters • Common mode parameters • Differential mode parameters • Current mode logic (CML) buffer • Relate to parameters • Modeling & simulation • Timing parameters • Clock recovery • Embedded clock • AC coupling • Common mode response • Issues with simulation • 8B10B encoding • DC balanced codes • Duty Cycle distortion • Cycle Differential Signaling

  3. Single Ended Signaling • All electrical signal circuits require a loop or return path. • Single ended signal subject several means of distortions and noise. • Ground or reference may move due to switching currents (SSO noise). We touched on this in the ground conundrum class. • A single ended receiver only cares about a voltage that is referenced to its own ground. • Electromagnetic interference can impose voltage on a single ended signal. • Signal passing from one board to another are subject to the local ground disturbance. • We can counteract many of these effect by adding more ground. • As frequencies increase beyond 1GHz, 80% of the signal will be lost. Differential Signaling

  4. Vref Vss Short line Vref Vss Rx1 Long line Vref Vss Rx2 Review of threshold sensitivity • The wave is referenced to either Vcc or Vss. Consequently the effective DC value of the wave will be tied to one of these rails. • The wave is attenuated around the effective DC component of the waveform, but the reference does not change accordingly. Hence the clock trigger point between various clock load points is very sensitive to distortion and attenuation. Tx Differential Signaling

  5. Differential Signaling • Any signal can be considered a loop is completed by two wires. • One of the “wires” in single ended signaling is the “ground plane” • Differential signaling uses two conductors • The transmitter translates the single input signal into a pair • of outputs that are driven 180° out of phase. • The receiver, a differential amplifier, recovers the signal as the difference in the voltages on the two lines. • Advantages of differential signaling can be summed up as follows • Differential Signaling is not sensitive to SSO noise. • A differential receiver is tolerant of its ground moving around. • If each “wire” of pair is on close proximity of one and other. electromagnetic interference imposes the same voltage on both signals. The difference cancels out the effect. • Since the AC currents in the “wires” are equal but opposite and proximal, radiated EMI is reduced. • Signals passing from one board to another are not subject to the local ground disturbances. • As frequencies increase beyond 1GHz, up to 80% of the signal may be lost, but difference still crosses 0 volts. • There are still loss issues for differential signaling but only come into play in high loss system. Most single ended systems assume approximately 15% channel loss. Differential Signaling

  6. Differential Signaling - Cons • The cost is doubling the signal wires, but this may not be so bad as compared to adding grounds to improve single ended signaling. • Routing constraint: Pair signals need to be routed together. • Differential signal have certain symmetry requirements that may pose routing challenges. Differential Signaling

  7. Differential Signal Parameters • Voltage on line 1 = a • Voltage on line 2 = b • Differential voltage d = a-b • Common mode voltage c= (a+b)/2 • Odd mode signal, o = (a-b)/2 • Even mode signal, e = (a+b)/2 • Signal on line 1 a = e+o • Signal on line 2 b = e-o • Useful relations; o = b/2; e = c Line 1 Line 2 Reference Differential Signaling

  8. Propagation Terms to Consider • Differential mode propagation • Common mode propagation • Single ended mode (uncoupled) propagation • This is when the other line is not driven but terminated to absorbed reflections. • Transmission line matrixes will reflect these modes. Differential Signaling

  9. Differential Microstrip Example SE: single ended = uncoupled Differential Signaling

  10. Differential Impedance • Coupling between lines in a pair always decreases differential impedance • Differential impedance is always less that 2 times the uncoupled impedance • Differential impedance of uncoupled lines is 2 times the uncoupled impedance. Differential Signaling

  11. Propagation Velocities • For TEM structures, (striplines) • Differential mode, Common Mode, and single ended velocities are the same • For Non TEM and Quasi-TEM structures (microstrip) • Differential mode, Common Mode, and single ended velocities and impedances are not the same. • Common mode can be converted to differential mode at a receiver and result in a differential signal disturbance. Differential Signaling

  12. Example of Common Mode • Line 1 and line 2 have the same DC offset. • This is DC common mode. • It can be defined as an average DC for time duration of many UI cycles value as well. • Line1 and line 2 have the same AC offset • This is AC common mode • AC common mode also result from time differences (skew) between signal on line 1 and line 2. This can result in AC common mode and differential signal loss. • The following slide will be used to clarify the above Differential Signaling

  13. Differential Signaling Basics • For long channels, at GHz frequencies, signal tend look like sine waves. • The artificial offset common to line 1 and 2 has an average of 1 and varies around that average by +/-0.1 in a period manor. Differential Signaling

  14. Individual signals • Devices need to have enough common mode dynamic voltage range to receive or transmit the waveforms. In this case the signals swing between -0.1 and 2.1. • The sine wave amplitude is 1 and peak to peak is 2. • Signal a and b is what would be observed with 2 oscilloscope probes Differential Signaling

  15. Differential Mode Signal • The differential amplitude is 2 and peak to peak is 4 which is 2 times the individual signal peak to peak amplitude. • Notice the distortions are gone. Differential Signaling

  16. Common Mode Signal • The DC common mode signal is 1 • The AC common mode signal is .2 v peak to peak • Some may specifications may call this 0.1 v peak from the DC average • We will add this common mode to the signals “a” and “b” Differential Signaling

  17. Add 150 ps skew to signal b • Waveforms do not look so good. • We even have what appears to be non-monotonic behavior. Differential Signaling

  18. Differential signal looks OK • However we lost differential signal amplitude. • It used to be 4 peak to peak and now is 3.562. Differential Signaling

  19. Common mode measurements are different • Average is still 1. Peak to peak is 0.944 but peak is 0.504 • AC common mode signals can be converted to differential Differential Signaling

  20. An escape from a BGA or connector pinsintroduces skew This is an example of skew compensation PWB structures that introduce Skew Differential Signaling

  21. Bends introduce skew Back to back bendscompensate for skew from frequencies below 2 GHz. Back to back bendscompensate for skew from frequencies below 2 GHz. Differential Signaling

  22. More Terms: Balanced and Unbalanced • Good Agilent Technologies article on balance and unbalanced signaling • http://we.home.agilent.com/upload/cmc_upload/tmo/downloads/EPSG084733.pdf • Unbalanced signaling in reference to ground • Balanced signaling is referenced only to the other port terminal. • If each channel is identical, then this suggests a virtual AC ground between the two terminals. It is often useful to allow this AC ground to be a DC voltage to biasing devices. Differential Signaling

  23. Ethernet 10/100BASE-T example Filter Transformer 50 W 50 W 50 W 50 W Common-mode choke Balanced Unbalanced Differential Signaling

  24. Low Voltage Differential Signaling: LVDS • 200MHz – 500 MHz Range • Published by IEEE in 1995 • Lacks robustness for GHz Signaling • Well suite distributing system clocks • Good noise margin • Common mode impedance has wide range provide buffer design flexibility • Differential impedance is optimize around 100 W • Differential receiver switching thresholds are tighter than for single ended logic. • Most device require external termination and bias resistors • Does not have capacitance or package spec. This severely limits GHz operation Differential Signaling

  25. Current Mode Logic • Emerging technology • No real spec yet but can infer operation from spec’s like PCI Express™ , Infiniband™, USB, SATA, etc. • Tx and Rx lines are separate • The Tx driver steers current between the differential terminals • AC coupling between Tx and Rx with a series capacitor provides common mode design flexibility • Termination is in buffers. This may require compensation or a band gap reference to insure a tight resistance range. Differential Signaling

  26. Example of Simple CML Differential Behavioral Circuit This exponent determines wave shape Vcc Balance between for FET switch I_source Positive Terminal This switch time offset Negative Terminal r_termp, C_term r_termn, C_term 2nd lecture Differential Signaling Vss

  27. Vcc I_source Example of Sensitivities: I, balance, C More prominent for faster edges Differential Signaling

  28. Vcc I_source Example of Sensitivities: Slew, Skew, R R/F slew +/skew Differential Signaling

  29. Serial Differential • GHz transmission will have many UI’s of data in transit on the interconnect at any points in time. • Hence it becomes useful to think of this as serial data transmission. • Often multiple single channels are ganged in parallel to achieve even higher data throughput. Differential Signaling

  30. AC coupling issues • Series capacitors can build up charge difference between differential terminals for the following reasons. • Unequal numbers off zero and ones • Duty cycle (UI) distortion. • The solution is to use a data code that is “DC” balanced. • 8B10B (8 bit 10 bit) with disparity is one such code • Tight UI control is a basic requirement for keeping the signal eye open Differential Signaling

  31. Eye Diagram • The eye diagram is a convenient way to represent what a receiver will see as well as specifying characteristics of a transmitter. • The eye diagram maps all UI intervals on top of one and other. • The opening in eye diagram is measure of signal quality. • This is the simplest type of eye diagram. The are other form which we will discuss later Eye Diagram Differential Signaling

  32. Creating eye diagram • Plot periodic voltage time ramps (saw tooth waves) on x verses the voltage wave on Y. • Can be done with Avanwaves expression calculator and can be saved in a configuration file. Differential Signaling

  33. Create ramp with expression builder Start of relative eye position Time of eye start Unit Interval Differential Signaling

  34. Copy Ramp to X Axis • Use middle button to drag ramp to Current X-Axis Differential Signaling

  35. Voltage and period volt-time ramp Differential Signaling

  36. Clocking • The one thing omitted in the suggests in the previous slides on eye diagrams was the “chop” frequency. • We assumed it was UI. This is simple for simulation. Time marches along and all signals start out synchronized in time. This is not true for real measurement since edges will significantly jitter and make it difficult to determinate where the exact UI is positioned. • Presently, there are basically two forms of GHz+ clocking • Embedded clocking • Forwarded clocking Differential Signaling

  37. Embedded clocking • This what is used in Fiber Channel, Gigabit Ethernet, PCI Express, Infiniband, SATA, USB, etc. • The clock is extracted from the data • There is requirement that data transitions are at a minimum rate. 8B/10B guarantees this. We discuss this in more detail later. • A phase interpolator is normally used to extract the clock from the data. We discussed the phase interpolator in the clocking class. The phase interpolator is tied to the PCI Express-like jitter spec: Median and Jitter outlier. Differential Signaling

  38. Jitter Median and Outlier Spec • Eye opening is defined from a stable UI. • Jitter median used to determine a stable UI • It is used as a reference to determine eye opening • Jitter Outlier is used to guarantee limits of operation UI Jitter outlier Jitter Median Eye diagram Differential Signaling

  39. Forwarded Clocking • The Tx clock is sourced and received down stream. The clock is a Tx data buffer synchronized with the Tx data bits. • A synchronization or training sequence on a data line is used to adjust the receiver clock so that it is in phase synchronization with the data. • The caveat is that the actual data clock lags the real data by a few cycles. • The whole idea is that the jitter introduced over these cycles would be smaller than the jitter associated with two the PLLs used to provide base clocks for an embedded clock design. Differential Signaling

  40. Aspects of AC coupling • We will explore issues with AC coupling with a simulation example. • First we will create a simple CML differential model • Next we will tie it to a differential transmission line and a terminator. • Assignment 7 is to reproduce these effects with a HSPICE program. The output Avanwaves with a power point story summary what you will hand in. • The basis for our work will be last semesters testckt.sp deck Differential Signaling

  41. Behavioral Data Model – Example 3rd lecture 12 bit of repeating data010101 001001 … v(t) data UI = 500 psTr=Tf=100ps Wave shape* Rterm=50 Cterm=0.25pf Vswing = 800 mV I=Vswing/(50||50)/2 * Refer to first course Differential Signaling

  42. AC coupled Differential Circuit AC coupling caps are normally larger, but are scaled down to illustrate common mode effects Differential Signaling

  43. Top Level HSPICE CODE Modified Convenience Differential Signaling

  44. No initial conditions on DC blocking caps • 300 ns of simulation time! • Cblkn pkg2_nb pkg2_n 1nf $ic=400mv • Cblkp pkg2_pb pkg2_p 1nf $ic=400mv • 101010 101010 repeating 12 bit pattern Reproduce this at package 2 (receiver) Differential Single ended Differential Signaling

  45. Set IC to Vswing/2 Reproduce this at package 2 (receiver) Differential Single ended Differential Signaling

  46. Not completely fixed • Initial voltage for D+ and D+ is not 0 so there is a step response when the wave reaches the receiver. • We can fix this by multiplying both “n” and “p” control waves for the VCR (voltage controlled resistor) by 0 for the first cycle. • This forces the DC solution at the other end of the line to 0 volts differential. Differential Signaling

  47. Insure both legs start at same voltage Qualifying voltage Qualifying voltagen control voltage Qualifying voltagep control voltage Differential Signaling

  48. Results – Pretty good • May have to ignore first 1-2 cycles Reproduce this at package 2 (receiver) Differential Single ended Differential Signaling

  49. Now lets change bit pattern Reproduce this at package 2 (receiver) • 100000001010 • The pattern creates a DC charge to be built up in the cap • The solution is to create a code that has equal amount of 1’s and zeros. This is the rational for 8bit 10 bit (8b10b) coding Differential Single ended Differential Signaling

  50. Crossing Offset • The crossing offset is the horizontal line that is in the vertical center of the eye and it should be at 0 volts for a differential signal. • The amount of offset is the average DC value. A simple approximation is one minus the ratio of one’s to zeros times the received vswing/2. • This does not included edge shape effects Differential Signaling

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