FPGA System Design Practice

1. FPGA System Design Practice Trong-Yen Lee http://www.ntut.edu.tw/~tylee E-mail: tylee@ntut.edu.tw Tel: 2771-2171ext.2251 Office: 綜科館302 Office Time: AM 9:00-12:00 (三)(五)

2. Book and References • Text Book: • Advanced Digital Logic Design Using Verilog, State Machines, and Synthesis for FPGAs • Reference book or papers • Wayne Wolf, FPGA-Based System Design, Prentice Hall, 2004. • Rapid System Prototyping with FPGAs by R.C.Cofer and Ben Harding, Newnes, 2006. • hppt://www.xilinx.com/support/support.htm

3. Course Outline(1/4) • 第一週--Chapter 1. Introduction • 第二週--Chapter 2. Digital Logic Design Using Hardware Description Languages; • Lab 1 - Digital Circuits Design By Xilinx ISE • 第三週--Chapter 2. Digital Logic Design Using Hardware Dscription Languages; • Lab 2 - Module-Based Digital Circuit Design and Verification • 第四週--Chapter 3. Introduction to Verilog and Test Benches

4. Course Outline (2/4) • 第五週--Chapter 4. High-Level Verilog Coding for Synthesis • Lab 3 - Tutorial using HDL Based Design • 第六週--Chapter 4. High-Level Verilog Coding for Synthesis • 第七週--Chapter 5. State Machine Design • 第八週--Chapter 5. State Machine Design • Lab 4 - Design a 4-bit up-down Counter • 第九週--期中考

5. Course Outline (3/4) • 第十週--Chapter 6. FPGA and Other Programmmable Logic Devices • 第十一週--Chapter 6. FPGA and Other Programmmable Logic Devices • Lab 5 - Design and Implementation • 第十二週--Chapter 7. Design of a USB Protocol Analyzer • 第十三週--Chapter 7. Design of a USB Protocol Analyzer

6. Course Outline (4/4) • 第十四週--Chapter 8. Design of Fast Arithmettic Units • 第十五週--Chapter 8. Design of Fast Arithmettic Units • 第十六週--Chapter 9. Design of a Pipelined RISC Microprocessor (Option): Term Project(一) • 第十七週--Chapter 9. Design of a Pipelined RISC Microprocessor (Option): Term Project(二) • 第十八週--期末考

7. Score • 平時成績(包含出席、作業、平時實驗及評量成績、Term Project等) 40% • Mid-TermExam. 30% • Final Exam. 30%