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An Overview of a 20Msps 12bit Pipelined ADC

An Overview of a 20Msps 12bit Pipelined ADC. Dr. Chris Hutchens SSC – San Diego Oklahoma State University. Outline. Outline Con’t. Introduction/Motivation. ADC Specification Review. ADC Specification Review. Line fit of the x-fer function. ADC Specification Review. Ideal Flash Error.

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An Overview of a 20Msps 12bit Pipelined ADC

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  1. An Overview of a 20Msps 12bit Pipelined ADC Dr. Chris Hutchens SSC – San Diego Oklahoma State University

  2. Outline

  3. Outline Con’t

  4. Introduction/Motivation

  5. ADC Specification Review

  6. ADC Specification Review Line fit of the x-fer function

  7. ADC Specification Review

  8. Ideal Flash Error

  9. Pipeline Overview

  10. Pipelined Stage Conversion

  11. Error Correction

  12. Error Correction

  13. Error Correction

  14. Error Correction (Con’t)

  15. Residual Voltage Errors

  16. T/H Topology and Noise Flip Around Charge Redistribution

  17. Auto-Zero MDAC Schematic

  18. MDAC Noise

  19. Flash ADC Offset must be reduced by 5 or 6 to ensure yield.

  20. Two Phase Timing

  21. Two Phase Timing

  22. Amplifier Requirements

  23. Amplifier Requirements

  24. Amplifier Summary

  25. Amplifier Summary

  26. Amplifier Summary

  27. Amplifier Summary

  28. Amplifier Summary

  29. Amplifier Summary

  30. Amplifier Summary

  31. Comparator

  32. Boosted Switches Conceptual Bias Scheme

  33. Issues remaining Areas

  34. Individual Focus Areas

  35. Immediate Pending Tasks

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